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McBSP received bytes are repeated

lijesh k
Intellectual 420 points

Hi,

I am testingMcBSP Sample code to use it in EDMA mode.

C:\dvsdk_1_01_00_15\pspdrivers_1_10_03\packages\ti\sdo\pspdrivers\system\dm6437\bios\evmDM6437\audio\sample

I have used EVM DM 6437 as slave and an FPGA as Master.

The data received on 6437 is correct. But in FPGA side the each byte is received twice.

Eg: I am sending 1,2,3,4..200 From DSPto FPGA and 1,2,3,4... 200 from FPGA to DSP

The received buffer in DSP is correct (1,2,3,4....200)

In the FPGA the received buffer is (1,1,2,2,3,3,4,4,..... 100,100)

Please help ..

Thanks

Lijesh

  • 0
    TI__Expert 7290 points

    Lijesh,

    Let me understand the issue correctly. If you use the DM6437 as a transmitter and as a receiver then you are able to receive the data as per the expectation.

    Instead of DM6437, if you use the FPGA at receiver end, then the data will be received twice. Am i right?

    If this is the case, could you tell me what is the difference between these two setups with respect to software configuration and the hardware?

    Regards,

    Sandeep K

  • 0 in reply to Sandeep Krishnaswamy
    Intellectual 420 points

    Hi Sandeep,

    If I have tried loopback in DM6437, It is working.

    Now I am Using DM 6437 as slave(DMA Interrupt) and FPGA as Master.

    The received buffer in DM6437 is correct.

    In FPGA the data is not received properly. Every byte is received twice.

    So only half of the data is received in FPGA master.

    DSP Slave sends 1,2,3,4,5,6,7,8,9,0 (10 bytes)

    FPGA Master received 1,1,2,2,3,3,4,4,5,5 (10 bytes) expected data is (1,2,3,4,5,6,7,8,9,0)

    In FPGA I am generating the CS and clock. The FPGA program received correct data  when I used CSL and polling program on DSP.

    Thanks

    Lijesh

  • 0 in reply to lijesh k
    Intellectual 420 points

    Hi,

    The issue is solved by reducing the clock speed on FPGA (Master) side.

    Thanks

    Lijesh