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DDR3 Trace spacing

Kika
Intellectual 420 points 


Hello,

I am sorry for asking too many questions on DDR3.
There is some confusion in understanding the datasheet parameter on Trace spacing.
The datasheet(SPRS717B) pg170 "Table 5-59. CK and ADDR_CTRL Routing Specification" 
16th parameter says "Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing shoulb be 3w MIN"
but the footnote 10 says "Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length"
what could be meaning of "(w)"? does it mean the MIN 3w = 1250 mils?
which means the MIN allowed trace spacing is 1250 mils?

Regards,
  • 0
    TI__Guru 63415 points

    The “w” parameter was defined as the signal trace line width in the PCB Stackup Specifications table.  This table was provided earlier in the DDR routing guidelines.

    Let’s assume your PCB design uses a typical trace width of 4 mils to achieve the expected trace impedance.  The 16th parameter in the CK and ADDR_CTRL Routing Specification table indicates the recommended center to center spacing of ADDR_CTRL to other ADDR_CTRL signals would be 3w or 12 mils.  However, note 10 provides an exception that allows this parameter to be reduced to w or 4 mils for up to 1250 mils of routed length.  This exception is provided to allow reasonable signal routing under the processor and memory devices.

    Regards,
    Paul