TMS320DA828/808 McASP0's Maximum throughput

Rajarama M Bhat

Hi,

Following page provides the throughput numbers for McASP in c674x.
http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_Multichannel_Audio_Serial_Port_(McASP)_Throughput_and_Optimization_Techniques
In our system we plan to have decoders from following page:
http://software-dl.ti.com/dsps/dsps_public_sw/codecs/C674X_Audio_Codecs/01_00_001/index_FDS.html
At one instant the TI-chip might need to have upto 4 decoder instances since there is a possibility of getting 4 streams at a time. We will be using TMS320DA828/808 as the SoC.
So keeping in mind all of the above(when memories are shared between decoders and drivers) can somebody suggest me how to find out the maximum datarate possible with one data line of McASP0, when McASP0 is configured to receive the data.

Thanks,
Rajaram

over 13 years ago

0 Urmil Parikh over 13 years ago

TI__Intellectual 1870 points

Hi,

We have used McASP to get input till 192 kHz over single serializer. that should be sufficient for 4 decoder instamces.

0 Rajarama M Bhat over 13 years ago in reply to Urmil Parikh

Intellectual 550 points

Hi Urmil,

Thank you for the response.

Can we assume 192khz=192*2(channels)*32(max bits/sample)=12288000 bits ?

Thanks,

Rajaram

0 Urmil Parikh over 13 years ago in reply to Rajarama M Bhat

TI__Intellectual 1870 points

Yes.

0 Rajarama M Bhat over 13 years ago in reply to Urmil Parikh

Intellectual 550 points

Hi Urmil,

Thank you for the reply.

Can you please let me know under what settings you were able to achieve 192khz?

For example in the following page:http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_Multichannel_Audio_Serial_Port_(McASP)_Throughput_and_Optimization_Techniques

"Competing Traffic, EDMA Background Activity Using Same TC -McASP Concurrent Data, 4 TX/RX Serializers, Same TC Used for Background Activity-McASP Concurrent Test with Element size=32 bits with FIFO enabled-300Mhz CPU-L2 with TX/RX EVT DMA ratio=6" will give 19mbps

Thanks,

Rajaram

0 Urmil Parikh over 13 years ago in reply to Rajarama M Bhat

TI__Intellectual 1870 points

In our use case it was using a properietory framework that involved input as I mentioned, followed by an audio decoder, audio post processing chain and output being driven through 4 McASP serializers at 48 kHz. We used PRU instead of EDMA for serving McASP events.

Other settings: McASP FIFO were enabled, L2 cache was enabled (64 K), serializers were configured in 32-bit I2S mode.

0 Rajarama M Bhat over 13 years ago in reply to Urmil Parikh

Intellectual 550 points

Hi Urmil,

Thank you for the reply.
In SoC TMS320DA828,which we are using, there are no PRUSS. So we will have to use EDMA for serving McASP events.Is that understanding correct?
So now, without PRUSS, will we be able to achieve 12288000 bits over single serializer(considering above said circumstances)?

Thanks ,
Rajaram

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TMS320DA828/808 McASP0's Maximum throughput