Hello,
I have seen all of the earlier posts regarding the power-down sequence, including this one: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/146484.aspx. However, I am not satisfied with the answer.
We have a design which, like the eval board, uses an FPGA to control the power sequencing for the DSP. The reset protocol used on our design is the same as that is used on the eval board, and does not include any power-down sequencing. Oviously, it is not possible to sequence off DSP power rails when the power inputs are removed, as with a hard shut-down. And power cannot be sequenced off properly, as per the datasheet, if a POR is asserted due to a loss of any of the rails other than that which should be removed first according to the sequencing requirements. So the only plausible scenario for implementing a power-down sequence as it is defined in the datasheet is if a power-on reset is asserted for reasons other than a power failure. So my question is: How important is it really to employ a power-down sequence for the single situation that would allow it, when all other situations make it impossible?
Thanks.
-Courtney