Hi:
This is regarding the L1/L2 memories on the OMAPL132 document SPRS762 (Aug. 2011). On page 20 we have DSP ROM, L1P, and L1D and L2 at certain addresses in DSP memory. Clearly the DSP uses these addresses when accessing these memories.
Now, on page 22, the same memory locations are at different addresses and are not specifically under DSP memory. I am guessing that when the ARM or other peripherals access these memories then they have to use these addresses. Could you please clarify, and also point to relevant documents that explain this?
Thanks a lot!
Cheers,
Mushtaq