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AM335x (Beaglebone) execution speed.

Yovi Oktofianus
Prodigy 85 points
Other Parts Discussed in Thread: OMAP3530

Hi,

I'm running a code in Baremetal mode using starterware and trying to execute certain low level operation if possible under 1 us.

I did some simple test on simple instruction like the below snippet and found out that the below snippet executes more than 3us :

unsigned int motors[16];
_Bool motorsEnabled[16];
static void test(void){

motorsEnabled[10] = TRUE;
motors[10] = 1500;
unsigned int start = ticks;
if(motorsEnabled[10] && (abs(start - motors[10]) < 7))
{
}
GPIOMultiplePinsWrite(GPIO_1_INSTANCE_ADDRESS, 3 << LED_1, 0);
unsigned int end = ticks;
UARTprintf("Start: %d ", start);
UARTprintf("End: %d ", end);
UARTprintf("Dist: %d ", end-start);

}

ticks is just a macro that read Timer4 counter register, Timer4 has been set to use 24Mhz input clock. The 3 us figure that I got is based on the difference between start and end devide by 24.

If i understand correctly by looking at bootloader code, beaglebone should runs at 720Mhz (Is powering by USB affecting this speed). My expectation might be wrong, but I'm expecting that with the core speed of 720Mhz, the instruction should be bellow 1 us, is my expectation correct? Any way to speed up the execution?

Please bear with me since this is the first time I'm dealing with SoC, previouslly just play around with simple uC that is not as complex as AM335x.

Any explanation is greatlly appreciated.

Regards,

Yovi

  • 0
    Prodigy 85 points

    Any update on this matter?

    I check the disassembler and the above codes (within start - stop) is only around 10 assembly instruction. How can a processor that runs on 500 mhz (Beaglebone on USB powered) execute it within 3 microseconds.

    Please gave me some ideas whats wrong...

  • 0 in reply to Yovi Oktofianus
    Intellectual 800 points

    Last week I also tried to time a particular function.  I found that I can get the BeagleBone to run my bare-metl StarterWare code in 3 different modes depending on how it powers up.  I wrote code to dump various registers to the Uart to determine what the clock speed and cache conditions were.

    Test conditions I used:

    1) power up without a boot SD card.  CPU runs at 500 MHZ, no I-cache, no D-cache.  My test code runs at 18ms

    2) boot Linux off SD on USB power, then halt it. CPU runs at 500MHZ, I-cache enabled, D-cache disabled.  Test code runs at 2.6ms.

    3) boot Linux off SD on 5V power, then halt it. CPU runs at 720MHZ, I-cache enabled, D-cache disabled.  Test code runs at 2.4ms.

    The times were determined by toggling a LED around the test code and looking at that with a scope, as well as using dm timer 2. 

    Beware that the Linux boot sets the timer pre-scaler, so I had to turn that off in my timer initialization code.

    Hope this helps.

  • 0 in reply to Gerard Belanger
    Prodigy 85 points

    Hi Gerard,

    Thanks for your reply, the cache things is the clue, I saw similar problems for OMAP35 processor in this thread:

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/93065.aspx

    I also found some details in 1st section Starterware documentation about MMU and cache:

    http://processors.wiki.ti.com/index.php/StarterWare_02.00.00.05_User_Guide

    And I found out how to enable cache and MMU in demoMain.c of starterware examples.

    I will try it at home and I will post the result.

    Cheers,

    Yovi

  • 0 in reply to Yovi Oktofianus
    Intellectual 895 points

    Dealing with all the caches and the MMU with the OMAP3530 bare metal was quite complex.
    Back then, I had the impression that it's not intended that the OMAP3530 is used bare metal with Code Composer.

    Starterware for AM335x sounds quite promising! But never forget to verify the performance!
    http://www.ti.com/tool/starterware-sitara 

  • 0 in reply to MGun
    Intellectual 800 points

    After my success with the instruction cache, I brought the cache startup from the cache_mmu StarterWare example into my test application.

    At 500 MHz, it improved the timing from 2.6ms with i-cache alone, to 60us.  So in my application the D-cache made a 40x improvement.

    The next step for me will be to see if SYS/BIOS supports theD-cache.

    Gerry Belanger

  • 0 in reply to Gerard Belanger
    Prodigy 40 points

    Hi Gerard,

    can you show your code?

    I also want to know exactly time to access OCMC RAM and DDR2 RAM. So with your code and your timing, I can compare with my result and theory about latency access Ram.

    Wait your answer, thanks

    Regard,

    Vinh Hung Hoang

     

  • 0 in reply to Vinh Hung Hoang
    Intellectual 800 points

    Vinh,

    I don't think my code will do you any good.  What I did was time an application routine using two methods. 

    First I set up a dmtimer to time the call to the application routine.

    Second, I put LED toggles before and after the call as a sanity check on the numbers the timer gave me. This I scoped.

    I also did a calibration run on the led toggles so I could remove that overhead from the timing calculation.

    So I was not doing memory access timing per-se, but simply timing an application function.  Then I was able to play with cache settings, and determine the effects.

    I also wrote some reporting code to read some PRCM PLL control registers to verify the cpu timing.

    All pretty straightforward.  But not, I gather what you were looking for.

    Gerry Belanger

  • 0 in reply to Gerard Belanger
    Prodigy 20 points

    I have the same problem, the code executes more than 80mS,  but I'm expecting that with the core speed of 720Mhz, the code should be bellow 1 mS.

    I am using AM335X_StarterWare_02_00_00_07.

    I have enable the MMU and cache in main routine. 

    /* Setup the MMU and do necessary MMU configurations. */

       MMUConfigAndEnable();

       /* Enable all levels of CACHE. */

       CacheEnable(CACHE_ALL);

    why?

    Regards,

    defu.luo


  • 0 in reply to defu luodefu
    Prodigy 20 points

    My code like below:

        unsigned int tmrcnt;

        unsigned int cnt;

       CPU_TS_TmrInit(); // timer2 init

        cnt = 720000;

        tmrcnt = CPU_TS_TmrRd();  // read original count

        GPIOPinWrite(SOC_GPIO_1_REGS, 26, GPIO_PIN_HIGH);  // turn on led

        while(cnt--);

        GPIOPinWrite(SOC_GPIO_1_REGS, 26, GPIO_PIN_LOW);  // turn off led

        tmrcnt = CPU_TS_TmrRd() - tmrcnt;  // calculate execute time

        UARTPuts("\n\rtmrcnt : ", -1);

        UARTPutNum(tmrcnt);

        UARTPuts("\n\r", -1);

    I am using AM335X_StarterWare_02_00_00_07.

    enabling the MMU and cache in main routine. 

    /* Setup the MMU and do necessary MMU configurations. */

       MMUConfigAndEnable();

       /* Enable all levels of CACHE. */

       CacheEnable(CACHE_ALL);

    Regards,

    defu.luo

  • 0 in reply to Gerard Belanger
    Prodigy 35 points

    hi , I am a really new chip learner, I want to run bare metal  test about beaglebone , I follow this link :http://wiki.osdev.org/ARM_Beagleboard and http://stackoverflow.com/questions/9142951/hello-world-bare-metal-beagleboard
    None of them works, I cannot get any output after I type command "go 0x8200_0000" in U-boot. Can you tell me how to do a bare metal test in beaglebone.

    I also want to know how do u set the cache (enable and disable) , can you tell me the methord to set and to check the status of the cache. 

    Regards

    Wei