Hello,
I am designing board based AM3359 and in my system I am using 16MBytes NOR Flash and 128MBytes NAND Flash. Both will be operating in 16bit - multiplxed mode.
I came up with following pin allocation, I will be thankful if someone verify or finds anything wrong please let me know before I do board design.
Thanks.
Looking For: 16-bit NOR flash access, 16 bit-bit NAND flash access
PART # NOR - 128Mb Parallel NOR Flash: JS28F128J3F75A
NAND - K9F1G16X0M
NAND INTEFACE: x16 BIT MODE
----------------------------------------------
GPMC_AD[15:0] => IO[15:0] (NAND FLASH)
GPMC_BE0n_CLE => CLE (NAND FLASH)
GPMC_ADVn_ALE => ALE (NAND FLASH)
GPMC_CS1n => CE (NAND FLASH)
GPMC_OEn_REn => RE (NAND FLASH)
GPMC_WEn => WE (NAND FLASH)
GPMC_WPn => WP (NAND FLASH)
GPMC_WAIT1 => R/B (NAND FLASH)
PRE (NAND FLASH) <= pull to high
NOR Interface: x16 bit mode
----------------------------
GPMC_AD[15:1] => 16BIT LATCH 74LCx16373 - ADDRSS IS LATCHED BY GPMC_ADVn_ALE => DEMUX_A[23:1] => A[16:1] (NOR FLASH)
GPMC_A[22:16] => A[23:17] (NOR FLASH)
GPMC_AD[15:0] => DQ[15:0] (NOR FLASH)
GPMC_CS0n => CE0 (NOR FLASH)
=> CE1 (NOR FLASH)
=> CE2 (NOR FLASH)
=> RPn (NOR FLASH) <= System Reset
GPMC_OE_REn => OEn (NOR FLASH)
GPMC_WEn => WEn (NOR FLASH)
GPMC_WAIT0 => STS (NOR FLASH)
=> BYTEn (NOR FLASH) <= PULL-HIGH(x16)
=> VPEN (NOR FLASH) <= PULL-HIGH