L1 and L2 SRAM.

Mushtaq Syed

Other Parts Discussed in Thread: OMAPL138

Hi:

If the L1P, L1D and L2 on C674x on the OMAPL138/L132 are programmed as SRAMs, instead of cache memories, then do they all have the same speed or is the L1 SRAM faster than the L2 SRAM?

Thanks a lot!

Cheers,

Mushtaq

over 14 years ago

0 Brad Griffis over 14 years ago

TI__Guru*** 125430 points

You'll achieve single cycle access to L1. A cache miss will be about 10 cycles to fetch from L2. An L2 miss will be 100-200 cycles. I strongly suggest keeping at least some amount of L1 cache in the system if you are dealing with any external memory.

0 Mushtaq Syed over 14 years ago in reply to Brad Griffis

Expert 1140 points

Hi Brad:

Thanks a lot!

I am wondering if the numbers you have quoted are for L1 and L2 programmed as cache memories. Is this correct?

We wont be using external memories. We want to use the L1 and L2 memories as SRAMs. Then will we have single cycle access to both the SRAMS?

Thanks a lot!

Cheers,

Mushtaq

0 Brad Griffis over 14 years ago in reply to Mushtaq Syed

TI__Guru*** 125430 points

See Table 3-2. L1D Performance Parameters (Number of Stalls) of the Cache User's Guide.

0 Mushtaq Syed over 14 years ago in reply to Brad Griffis

Expert 1140 points

Hi Brad:

Thanks a lot!

I will look into it.

Thanks again!

Cheers,

Mushtaq

Processors

Processors forum

L1 and L2 SRAM.