Memory section and loadalign

Jean-Baptiste Theou

Hi,

One of my demo application is based on "Image Processing Demo" platform and .cfg. My application work fine, but to be able to optimize my memory map in the future, I looking for memory map and loadalign value. I can't find any information about loadalign value. For exemple, on the demo .cfg, we have :

Program.sectMap[".vecs"] = {loadSegment: "MSMCSRAM_MASTER", loadAlign:1024};

What is the reason of this 1024 value ? Where I can find this information ? And why put .vecs section on shared memory rather than on L2SRAM ?

I take this example, but there are many other sections (NDK section, etc ... ).

Thanking you in advance for your advice, because I am a little lost with this memory map.

Best regards,

over 13 years ago

0 David Friedland over 13 years ago

TI__Mastermind 18320 points

Theou,

Can you provide information on exactly what TI software components you are using and what device you are programming?

0 Jean-Baptiste Theou over 13 years ago in reply to David Friedland

Intellectual 270 points

David,

Yes, of course. At the first time my post was on C66xx forum, so I didn't provide those information.

Target : 6678 on EVM6678LE

CCS version : 5.1.1.00031

MCSDK : 2.00.05.17

Thanking you in advance for your information.

0 David Friedland over 13 years ago in reply to Jean-Baptiste Theou

TI__Mastermind 18320 points

Sorry for the delay -- I am working to get an expert in touch with you.

Thanks for your patience.

Dave

0 Jean-Baptiste Theou over 13 years ago in reply to David Friedland

Intellectual 270 points

Dave,

No problem, I am working on an other topic right now ... No emergency.

Thank you for your help

Jean-Baptiste

0 Karthik Ramana Sankar over 13 years ago in reply to Jean-Baptiste Theou

TI__Intellectual 2415 points

Hi Jean,

More information about loadalign can be found in section 6.3.2 "Configuring Section Placement Using a SectionSpec" of the BIOS user guide, which can be found at:

<CCS_INSTALL>\bios_6_32_05_54\docs

Configuring a loadalign of 1024 bytes, specifies to the linker to allocate a memory block for .vecs section, whose starting address is 1024 byte aligned (10 LSB's of the address are zero). I think, the .vecs section is used to place the interrupt vector table.

The .vecs section contains code and not data, hence by putting .vecs in MSMC memory, we can shared this section among multiple cores (cores which run the same .out file). On the other hand, putting .vecs in local L2SRAM, will create separate images of this section in the local L2SRAM (this is not efficient), which will be accessed by the respective cores running the same .out file.

As a general rule for multiple cores running the same image, we can always put code (not self modifying code) in shared memory like MSMC, where as data sections can go into local L2SRAM or MSMC (we should have separate sections for each of the cores or we should protect the shared data section using mutexes).

I hope this helps.

0 Jean-Baptiste Theou over 13 years ago in reply to Karthik Ramana Sankar

Intellectual 270 points

Hi Karthik,

I have my answer with your answer.

Thank you very much

Regards

Processors

Processors forum

Memory section and loadalign