How to run h264vencApp6678 standalone demo on multi CPU

Hi Sunzhao,

You are right for creating "encoder1.cfg" for the 2-core case. "encoder1.cfg" would be a copy of "encoder0.cfg". Then, make the following changes in the .cfg files (assuming 2-core case and CIF resolution). topSliceLine and bottomSliceLine below specify the range of lines to be encoded by the corresponding core. Note that the number of lines per core must be multiple of 16.

encoder0.cfg:

topSliceLine = 0

bottomSliceLine = 144

NumCores = 2;

encoder1.cfg:

topSliceLine = 144

bottomSliceLine = 288

NumCores = 2;

For running the unit test, first load the same .out file on core 0 and core 1. Then, run core 0. After that, run core 1.

For codec unit test, we manually load the same .out file to individual cores. The task split for H.264BP encoder is using a slice-based approach, and each core's encoding region is specified via codec dynamic parameters: topSliceLine & bottomSliceLine (populated from the above encoder*.cfg files in unit test).

Thanks,

Hongmei

Hi Hongmei,

     Thanks for your reply!  But I think the slice-based approach is fit for encoder only.

It is a approach for dispatching task to multiple cores statically. Then I wonder how do

you balance the task dispatched to each core dynamically in decoder case.

Thanks a lot!

Sunzhao

Hi Hongmei,

       I run the program on 2 cores under you direct. But it block down.

The output message from each core is as below:

Core0:

Erase external (0x80000000) 1fe0000
Erase internal (0x00800000) 3fd00
DONE
[0] framesToEncode 10 from ..\..\..\Test\TestVecs\Input\test.yuv
TopSliceLine=0 BottomSliceLine=144 SingleCoreRun=0
ShmemTab initialized on Core 0

Core1:

Erase external (0x86000000) 1fe0000
Erase internal (0x00800000) 3fd00
DONE
[1] framesToEncode 10 from ..\..\..\Test\TestVecs\Input\test.yuv
TopSliceLine=144 BottomSliceLine=288 SingleCoreRun=0

Please help me check it, Thank you!

Sunzhao

Hi Sunzhao,

For both slice-based approach (e.g., H.264 BP Encoder) or pipeline-based approach (e.g., H.264 HP Decoder), our multi-core codec partitioning is using a Master-Slave(s) strategy. With a single .out for all the cores, framework/application determines the number of cores participated in multi-core encoding (or decoding), as well as the role (master or slave) of each codec instance.

The Data structure (IVIDMC_t) for multi-core codec interfacing with framework/application can be found in <mcsdk video install dir>\dsp\siu\ividmc\ividmc.h. As shown below, it specifies number of cores, core IDs, and core task ID (master or slave).

{

...

  /* Identification parameters, to be set by the framework */

  XDAS_Int32 ncores;    

  IVIDMC_TASK_e core_task_ID;

  XDAS_Int32 coreID;

} IVIDMC_t;

In MCSDK Video 2.0, framework is responsible for creation of both master and slave codec instances. Framework also determines upfront how many cores are needed for encoding (or decoding), which cores will participate, and their master/slave role. Then, when framework creates the master/slave codec instance, it passes such multi-core information in IVIDMC_t data structure (which is part of static params) to the codec. It is not expected that cores communicate with each other at create time. At run time, framework is also responsible for activating codec tasks on all the required cores at right time.

Thanks,

Hongmei

Hi Hongmei,

     Thank you very much for you reply! But I still can not run the standalone demo on 2 cores under

your direct. The issue is discribed above, can you help me check it? Thank you very much!

By the way, can you send the airshow_p1280x720_4Mbps.264 clip to my Email too? My mail

is tongxin45@163.com    Thank you!

Sunzhao 

Hi Sunzhao,

With the same change to encoder0.cfg and encoder1.cfg, I can run the test application of H264BP encoder on two cores. Please follow the steps below to run the test:

Hi Hongmei,

      Thank you very much for your reply!

      I can run the test application of H264BP encoder on two cores with my evm6678l and DSPC8681 now. But I still be confused about

questions below:

      1. Why must we do system reset /CPU reset for each cores before loading init.out?  When running on DSPC8681 test board, I noticed that

 if I do not do CPU reset, Core 0 will be blocked and the log message is :

          Erase external (0x80000000) 1fe0000

       2. I can only do CPU reset through JTAG interface with IDE (CCS) now. But for DSPC8681 card, how can we do that through PCIE utils(say dsp_loader)

 instead of using CCS? 

Sunzhao

Hi Sunzhao,

The procedure of step 1-6 in our earlier reply applies to evm6678l only.

For DSPC8681, can you please try with the following procedure? There is no system reset or CPU reset.

Hi Hongmei,

                I have tried several times under your directions, But it seems that the program does not work unless

I do CPU reset for both core0 and core1 on DSPC8681, My procedure is below:

1) Power-up PC along with DSPC-8681

2) do cpu reset to core 0 and then to core 1

3) Load and run the  init.out for initializing DDR and Ethernet HW

4) Load the test application .out for H264BP encoder to core 0 and core 1 (assuming  use 2 cores )

5) Run the test application .out for H264BP encoder on core 0, and then on core 1.

Otherwise, if I do not do cpu reset, Core 0 will be blocked and the log message is :           Erase external (0x80000000) 1fe0000

-----------------------------------------------------        

block here...

Will you please help me verify this issue. Or if it works in your side, will you please attach your .out file

for me to test? Thanks a lot!

Sunzhao

Hi Sunzhao,

We tried 2-core H264BP encoder unit test on DSPC8681, and it did require CPU reset on the participating cores. Below is the procedure we followed:

1. Power cycle PC along with DSPC8681

2. Load and run init.out on core 0

3. CPU reset on core 0 and core 1

4. Load H264BP encoder unit test .out on core 0 and core 1

5. Run core 0 and then core 1

To re-run the unit test, repeat steps 4 and 5. Steps 2 and 3 need to be run just once.

Thanks,

Hongmei

Hi Hongmei,

      For the reason that some application need do cpu reset before running, How can we

run them on DSPC8681 without help of CCS? That is , can we do dsp reset through the

PCIE interface instead of through a JTAG debugger with CCS?  In my opinion, we should not

always depend on JTAG debugger when the application is released. I have a "pcieboot_localreset_evm6678l.out"

in my hand which can be load to dsp memory through PCIE interface and run. But it seems that it 

still can not replace the "CPU reset" in CCS because the dual-core unit testing program still can not

work with it.

Thanks a lot!

B.R.

Sunzhao.

Yes. We can reset the DSP through PCIE, by writing to BOOTCFG & Power sleep control ( PSC) registers.

We have code for this part of the Desktop linux sdk. The alpha2 release of which is planned end of next week. ( 22nd June)

This  reset mechanism through PCIE, available in this release, does not do a full system reset. It resets all the modules except PCIE.

We will plan to update you on the release once it is available.

Can we download Desktop Linux SDK alpha1?

http://processors.wiki.ti.com/index.php/Desktop-linux-sdk_01.00.00.01_Getting_Started_Guide says:

Desktop Linux SDK: Release Notes: <release notes link: to be populated after web publish>