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PCIe loopback problems

Mark Swick

Intellectual 565 points

EDIT: MOVED TO INTEGRA Forum Per Poster Request - C.Courtney

I am attempting a PCIe loopback test similar to the PCIe example project in the PDK. I have a TMDXEVM6678L running a slightly modified version of the EP example. I also have an Integra C6 on our own CPE module running the RC side using code created by using the RC portion of the PCIe example project provided in the PDK for the DSP. There is a PEX 8617 PCIe switch between them (I believe I have this configured correctly). I am able to send the data from the RC to the EP and verify it through the code composer memory view and also can do a memory dump from the Wind River work bench tool and read the data in the DSP. At this point I have not yet written the data back to the RC. After writing the data back to the RC I see that the Activity status register in the RC indicates ”Inbound buffers are not empty”. I also have seen a master abort error set on the EP side, but not every time.

I attempt to read the DSP memory again and I cannot. Data abort error is indicated by the VxWorks shell. SIG_SYS_ERROR is indicated in the STATUS_Command register on the DSP (EP).

I CAN HOWEVER read the switch configuration via it’s BAR 0 address.

I then attempt the data back from the DSP side and get very peculiar results loaded into the dstBuf (0x62800000 is the address of the PCIe space I am attempting to read:

[0] unsigned int 0x94CD0C6E (Hex) 0x00818500

[1] unsigned int 0xEE908000 (Hex) 0x00818504

[2] unsigned int 0x94CD0C6E (Hex) 0x00818508

[3] unsigned int 0xEE908000 (Hex) 0x0081850C

[4] unsigned int 0x94CD0C6E (Hex) 0x00818510

[5] unsigned int 0xEE908000 (Hex) 0x00818514

[6] unsigned int 0x94CD0C6E (Hex) 0x00818518

[7] unsigned int 0xE8800000 (Hex) 0x0081851C

<- single stepped above this

<- run to completion returns results with every other word correct

[8] unsigned int 0x62800000 (Hex) 0x00818520

[9] unsigned int 0x00000008 (Hex) 0x00818524

[10] unsigned int 0x62800000 (Hex) 0x00818528

[11] unsigned int 0x0000000A (Hex) 0x0081852C

[12] unsigned int 0x62800000 (Hex) 0x00818530

[13] unsigned int 0x0000000C (Hex) 0x00818534

[14] unsigned int 0x62800000 (Hex) 0x00818538

over 13 years ago

0 Mark Swick over 13 years ago

Intellectual 565 points

Does the returned pattern of alternating data and base address indicate anything to anyone?

0 Steven Ji over 13 years ago

TI__Genius 12065 points

Mark,

I think we could focus on the error when writing data back from EP to RC first.

Could you please confirm there is no error after RC writes data to EP?

If so, could you check if both BUS_MS bit and MEM_SP bit are set in STATUS_COMMAND register in both RC and EP devices please?

When writing data to RC, the BARn register in RC should also be set to match the PCIe address from EP side. Otherwise, the packets will be rejected and error may be reported.

So could you please double check if the PCIe address coming from EP is what we expected (if the outbound translation in EP side is being used and being set correctly)?

And what is the setup of BARn (BAR0,1,etc) on RC side (matching the incoming PCIe address?) and if the data could be arrived on RC side internal memory correctly due to the configuration inside of RC please?

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

Steven,

Yes both the BUS_MS and MEM_SP are set on both sides. The inbound and outbound configuration are set such that I see write transactions arriving at the RC with correct address and data. Afew packets seem to have errors in the address as observed on the bus analyzer we are using. As far as reads go on the Integra we can capture one of a series of reads with an ack but no completion packet. I am assuming the rest of the series is stalled or aborted. I am not sure where the DSP is getting data but it is moving data to the dstBuf and about half looks correct. This maybe a cache issue. I am able to write and read back data from the RC to the EP correctly. We have not captured an NAKs or Completion pakets with unsupported requests that we can see.

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

Fullscreen 7245.RC_ConfigPreError.txt Download

0x51000000:  4e310900 00000007 01040100 00000000  *..1N............*
0x51000010:  00000000 00010000 00000000 00000000  *................*
0x51000020:  00000000 00000000 00000000 00000000  *................*
0x51000030:  00000003 00000000 00000000 00000000  *................*
0x51000040:  00000000 00000000 00000000 00000000  *................*
0x51000050:  00000000 00000000 00000000 00000000  *................*
0x51000060:  00000000 00000000 00000000 00000000  *................*
0x51000070:  00000000 00000000 00000000 00000000  *................*
0x51000080:  00000000 00000000 00000000 00000000  *................*
0x51000090:  00000000 00000000 00000000 00000000  *................*
0x510000a0:  00000000 00000000 00000000 00000000  *................*
0x510000b0:  00000000 00000000 00000000 00000000  *................*
0x510000c0:  00000000 00000000 00000000 00000000  *................*
0x510000d0:  00000000 00000000 00000000 00000000  *................*
0x510000e0:  00000000 00000000 00000000 00000000  *................*
0x510000f0:  00000000 00000000 00000000 00000000  *................*
0x51000100:  00000000 00000000 00000000 00000000  *................*
0x51000110:  00000000 00000000 00000000 00000000  *................*
0x51000120:  00000000 00000000 00000000 00000000  *................*
0x51000130:  00000000 00000000 00000000 00000000  *................*
0x51000140:  00000000 00000000 00000000 00000000  *................*
0x51000150:  00000000 00000000 00000000 00000000  *................*
0x51000160:  00000000 00000000 00000000 00000000  *................*
0x51000170:  00000000 00000000 00000000 00000000  *................*
0x51000180:  00000000 00000000 00000000 00000000  *................*
0x51000190:  00000000 00000000 00000000 00000000  *................*
0x510001a0:  00000000 00000000 00000000 00000000  *................*
0x510001b0:  00000000 00000000 00000000 00000000  *................*
0x510001c0:  00000000 00000000 00000000 00000000  *................*
0x510001d0:  00000000 00000000 00000000 00000000  *................*
0x510001e0:  00000000 00000000 00000000 00000000  *................*
0x510001f0:  00000000 00000000 00000000 00000000  *................*
0x51000200:  20000001 00000000 30000001 00000000  *... .......0....*
0x51000210:  40000001 00000000 50000001 00000000  *...@.......P....*
0x51000220:  60000001 00000000 70000001 00000000  *...`.......p....*
0x51000230:  a0000001 00000000 00000000 00000000  *................*
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0x51000250:  00000000 00000000 00000000 00000000  *................*
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0x51000280:  00000000 00000000 00000000 00000000  *................*
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0x510002e0:  00000000 00000000 00000000 00000000  *................*
0x510002f0:  00000000 00000000 00000000 00000000  *................*
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0x51000930:  00000000 00000000 00000000 00000000  *................*
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0x51000950:  00000000 00000000 00000000 00000000  *................*
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0x510009a0:  00000000 00000000 00000000 00000000  *................*
0x510009b0:  00000000 00000000 00000000 00000000  *................*
0x510009c0:  00000000 00000000 00000000 00000000  *................*
0x510009d0:  00000000 00000000 00000000 00000000  *................*
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0x51000a10:  00000000 00000000 00000000 00000000  *................*
0x51000a20:  00000000 00000000 00000000 00000000  *................*
0x51000a30:  00000000 00000000 00000000 00000000  *................*
0x51000a40:  00000000 00000000 00000000 00000000  *................*
0x51000a50:  00000000 00000000 00000000 00000000  *................*
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0x51000a80:  00000000 00000000 00000000 00000000  *................*
0x51000a90:  00000000 00000000 00000000 00000000  *................*
0x51000aa0:  00000000 00000000 00000000 00000000  *................*
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0x51000b00:  00000000 00000000 00000000 00000000  *................*
0x51000b10:  00000000 00000000 00000000 00000000  *................*
0x51000b20:  00000000 00000000 00000000 00000000  *................*
0x51000b30:  00000000 00000000 00000000 00000000  *................*
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0x51000ea0:  00000000 00000000 00000000 00000000  *................*
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0x51001020:  7ff00000 7ff00000 00000000 00000000  *................*
0x51001030:  00000000 00000040 00000000 000001ff  *....@...........*
0x51001040:  00035001 00000000 00000000 00000000  *.P..............*
0x51001050:  00807005 00000000 00000000 00000000  *.p..............*
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0x51001080:  30220008 00000040 004003c0 00000000  *.."0@.....@.....*
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0x51001200:  00000000 00000000 00000000 00000000  *................*
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0x510016a0:  00000000 00000000 00000000 00000000  *................*
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0x510016c0:  00000000 00000000 00000000 00000000  *................*
0x510016d0:  00000000 00000000 00000000 00000000  *................*
0x510016e0:  00000000 00000000 00000000 00000000  *................*
0x510016f0:  00000000 00000000 00000000 00000000  *................*
0x51001700:  010c0059 ffffffff 07000004 1b0f6400  *Y............d..*
0x51001710:  00030120 00000000 000103aa 00000500  * ...............*
0x51001720:  00000000 00000003 03a5fc11 08000410  *................*
0x51001730:  0001a102 0001afff 0001a0e2 00000000  *................*
0x51001740:  0000000f 00000000 4021702f 00217005  *......../p!@.p!.*
0x51001750:  00800000 00000000 00000000 00000000  *................*
0x51001760:  00000000 00000000 00000000 00000000  *................*
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I attempted to attach a dump of the configuration before the error on the RC side (Integra). may be you can find something?

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

The RC register dump seems fine. Could you also share the register setup on EP side as well?

Or could you share the example code on both RC and EP sides as what modifications you have done based on the PDK loopback example please?

One thing to note is that no matter Write or Read transactions from EP to RC, it is all outbound transactions for EP. So it is using the outbound translation registers set on EP side and inbound translation registers set on RC side, if EP initializes the transaction (Read or Write).

If you could see Write transaction from EP to RC arrived on RC correctly, the Read transaction from EP to RC should be very similar as well. I am not sure how you issue the Read/Write transactions from EP to RC, maybe some incorrect addresses/memory have been used. so any code related to it will be helpful. Thanks.

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

Fullscreen 7317.postConfig.dat.txt Download

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The above file is the dump of the DSP EP configuration. I created this file by usung the COde composer save memory option. I calculat the address by subtracting 2 from the line number and multipying by 4. The start is the Application space running trhough the config space as documented in the sprugs6a.pdf

The above file is the 6678 code as end point.

3465.RC_Code.zip

the Above file is the RC Integra code using vxWorks

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

Thanks a lot for posting the code.

I have one question about the "PCIeLoopback()" in "pcie_support.c" file on the EP side.

You said you are testing the loopback data flow which means RC writes data to EP and then EP writes data to RC.

But on the EP side, before waiting for the completion of RC writing to EP, there are already some activities on the EP PCIe port:

/***********************start of code***************************/

void PCIeLoopback(void)
{
    int i=0;
    uint32_t             *pcieBase;
    pcieBase = (uint32_t*) (LOCAL_OB_CONTRL_ADDR_FPGA + 0x8004);
    dstBuf[0] = pcieBase[0];

{
    for (i=0; i<PCIE_BUFSIZE_APP; i++)
    {
       dstBuf[i] = 0;
    }
    for (i=0; i<PCIE_BUFSIZE_APP; i++)
    {
       dstBuf[i] = pcieBase[i];
    }
    /**********************************************************************/
    /* Wait for a single message from the RC then echo it back            */
    /**********************************************************************/

    /* EP waits for the data received from RC */
    do {
      unsigned int key;

      /* Disable Interrupts */
      key = _disable_interrupts();

      /* Cleanup the prefetch buffer also. */
      CSL_XMC_invalidatePrefetchBuffer();

      CACHE_invL1d ((void *)dstBuf, PCIE_EXAMPLE_DSTBUF_BYTES, CACHE_FENCE_WAIT);
      CACHE_invL2 ((void *)dstBuf, PCIE_EXAMPLE_DSTBUF_BYTES, CACHE_FENCE_WAIT);

      /* Reenable Interrupts. */
      _restore_interrupts(key);

    } while(dstBuf[PCIE_BUFSIZE_APP] != PCIE_EXAMPLE_BUF_FULL);

    System_printf ("End Point received data.\n");

/***********************end of code***************************/

If the "pcieBase[]" is pointed to the PCIe data space (0x60000000~0x6FFFFFFF in C66x), "dstBuf[i] = pcieBase[i];" means you are reading something from PCIe data space (from remote device over the PCIe link) to the dstBuf.

In the header file, it looks like pcieBase[] is pointed to the PCIe data space ("#define LOCAL_OB_CONTRL_ADDR_FPGA (0x61000000)"). But I am not sure what is the role for "0x8004" here.

Besides, after waiting for the RC writing data to EP, the EP uses the same pcieBase[] to write data to RC as

    for (i=0; i<PCIE_BUFSIZE_APP; i++)
    {
      pcieBase[i] = dstBuf[i];
    }

Then I am not sure if it is really what you intend to do in this loopback testing.

Basically, when RC initiates the transfer (no matter Write or Read), the data being transferred to the PCIe data space in RC should be translated to the correct outbound PCIe address, which should match the EP BARn register and EP inbound translation address, then the data go to (or be fetched from) the EP dstBuf over the PCIe link.

When EP initiates the transfer (no matter Write or Read), the data being transferred to PCIe data space in EP should be translated to the correct outbound PCIe address, whcih should match the RC BARn register and RC inbound translation address, then data go to (or be fetched from) the RC dstBuf.

Please double check if it is the case in your project for both RC and EP sides. And if the pcieBase is pointed to the correct PCIe data space on both sides as well. Thanks.

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

I have since removed that code or actully moved it down below the wait for PCIE_EXAMPLE_BUF_FULL.

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

I attempted to attach this earlier but ut seemed to not be there.

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

Thanks for the updated source files.

1. In the following code, I could understand the "Read 1" section. It looks like the OB/IB on RC/EP sides are matching each other (PCIe address from EP after translation is 0x90000000, which is matching RC BAR1 register 0x90000000).

Do you see any error only after the first EP reads from RC please?

/******* Start **********/

pcieBase = (uint32_t*) LOCAL_OB_MEMORY_ADDR_BGPP;

// Read 1
for (i=0; i<PCIE_BUFSIZE_APP; i++)
{
dstBuf[i] = 0;
}
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
dstBuf[i] = pcieBase[i];
}

/******* End **********/

2. For the second part "Read 2", I am not sure which address you want EP to write to. pcieBase is pointed to other place and if I calculated correctly, the PCIe address after translation is 0x60008004, which is not matching to the RC BAR1 register (0x90000000). So you write the dstBuf data to some location over PCIe link and read the data back to EP.

I am not sure which PCIe device will accept this packet with PCIe address 0x60008004. I hope this write transaction does not change any configuration over the PCIe link (not changing the setup of PCIe Switch, RC or other system setup).

Do you see the error after Read 2 please?

/******* Start **********/

// Read 2
pcieBase = (uint32_t*) (LOCAL_OB_CONTRL_ADDR_FPGA + 0x8004);
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
    pcieBase[i] = dstBuf[i];
}

for (i=0; i<PCIE_BUFSIZE_APP; i++)
{
      dstBuf[i] = 0;
}
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
      dstBuf[i] = pcieBase[i];
}

/******* End **********/

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

The error seem to occur on the write back of the data from the DSP EP to the RC. By error I mean that the memory targeted by the write back to the RC from the EP is not written. I reserved a portion of memory at the 0xc0000000 address space NON cached. I never see data written back arrive. It also caused the RC to become unable to arite or read past the switch. After initialializing BAR0 of the RC this particular symptom went away. When the EP attempts to read from RC I have seen a single read captured by the analyzer sometimes with an ack but we have not captured any completion packet for the read as of yet. I am going to look through the old log we have captured and send you some later. Write now we are having problem capturing anything with the protocal analyzer.

0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

I was way off on my last reply I also injected an error on my code that I now have corrected.

/*****************************************************************************
* Function: PCIeLoopback
*/
void PCIeLoopback(void)
{
    int i=0;
    uint32_t             *pcieBase;
    /**********************************************************************/
    /* Wait for a single message from the RC then echo it back            */
    /**********************************************************************/

    /* EP waits for the data received from RC */
    do {
      unsigned int key;

/* Disable Interrupts */
key = _disable_interrupts();

/* Cleanup the prefetch buffer also. */
CSL_XMC_invalidatePrefetchBuffer();

CACHE_invL1d ((void *)dstBuf, PCIE_EXAMPLE_DSTBUF_BYTES, CACHE_FENCE_WAIT);
CACHE_invL2 ((void *)dstBuf, PCIE_EXAMPLE_DSTBUF_BYTES, CACHE_FENCE_WAIT);

/* Reenable Interrupts. */
_restore_interrupts(key);

} while(dstBuf[PCIE_BUFSIZE_APP] != PCIE_EXAMPLE_BUF_FULL);

System_printf ("End Point received data.\n");

    /* Loopback to RC what was written in the DST buffer.
       Write from EP to RC */
    /* if ((retVal = Pcie_getMemSpaceRange (handle, &pcieBase, NULL)) != pcie_RET_OK) {
      System_printf ("getMemSpaceRange failed\n", (int)retVal);
      exit(1);
    } */

{
pcieBase = (uint32_t*) LOCAL_OB_MEMORY_ADDR_BGPP;

/***********************************************************************************************************************************

HERE IS Where the ER

    for (i=0; i<PCIE_BUFSIZE_TEST; i++)
    {
    pcieBase[i] = dstBuf[i];
    }
   /* Mark that the buffer is full, so RC can process it */
    pcieBase[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_FULL;

/* Note on cache coherence: Write back is not necessary because pcieBase is in
peripheral address space instead of physical memory*/

    System_printf ("End Point sent data to Root Complex, completing the loopback.\nEnd of Test.\n");
}
// Read 1
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
   dstBuf[i] = 0;
}
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
   dstBuf[i] = pcieBase[i];
}
// Write and read to/from FPGA

/****** The following code is a test to see if reads and writes to the FPGA are succesful **/
pcieBase = (uint32_t*) (LOCAL_OB_CONTRL_ADDR_FPGA + 0x8000);
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
pcieBase[i] = dstBuf[i];
}

for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
   dstBuf[i] = 0;
}
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
   dstBuf[i] = pcieBase[i];
}
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
   dstBuf[i] = 0;
}
for (i=0; i<PCIE_BUFSIZE_TEST; i++)
{
   dstBuf[i] = pcieBase[i];
}

}

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

I am a little confused. I think you correct some error in the source code and the one attached above "7026.PCIe.zip" should be the latest code under testing.

The observations you described before is based on this current code or the previous code please?

In other words, do you still see any error happening with the current code on EP side please?

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

The current code I just sent, still has the pronblem that read and write transaction from the EP to the RC do not complete. After writing data to the RC, I attempt to veirfy by reading from both sides of the interface. Th EP reads return results similar to the results in my first post.

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

Steven,

We just got our PCIe Analyzer back up. We notice that the EP device our 6678 DSP sets the requester ID to 0x0000 for memory write and read requests. These requests start at bus 2 transition to bus 1 in the switch and arrive at the bus 0 of the switch which is the port to the RC. Does this cause a problem for completion packet from the RC to the EP?

We also noticed that our command status register has not set the POSTED_WR_EN bit. Is this also problem for writes?

Thank for your help.

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

The requester ID has the information of Bus/Device/Function numbers of the requester. Normally the Host/RC will enumerate the whole PCIe bus and assign the numbers to each device found. I think you probably do not have the enumeration process in your system, so the EP bus/device/function numbers remain all 0s.

Those ID numbers are used for ID routing based transaction (such as configuration transactions). For memory transactions (memory Read/Write), the addressing routing could be used and we may not care those ID numbers. But you have one switch between the RC and EP, it is probably the switch is configured to use ID routing for all the transactions.

One thing you could try is to remove the Switch and connect RC and EP directly via PCIe pins and try the application example you have for the loopback transactions. The bus/device/function numbers could use the default values on both RC and EP (but the configuration transactions from RC to EP may not be addressed correctly, so configure the registers by themselves). Then you could verify if the memory transaction is good in your example.

If you want to test with the Switch together, you could either run any enumeration process on RC (it could be Linux PCIe driver to enumeration the bus) or you could assign Bus number = 2 to the EP device in CFG_SETUP register and leave Device/Function numbers as 0s since it is the single device on Bus 2 with single function.Then we could run the applications again with the Switch to see if the transaction could be done correctly (completion packet should be routed back to the requester).

I think the POSTED_WR_EN bit is used for the internal bus master write within the device. It could be set as default value and you could try the tests above first. Thanks a lot.

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

More info:

We performed some config write to the DSP and it now provides the correct requester ID. We stil do not see completion packets for reads and the writes do not change target memory.

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

I tried your applications in our two-DSP setup (C6678 to C6678). I loaded your source code of EP directly to one DSP and modified the RC side (simulate the same setup) and loaded on another C6678 DSP.The PCIe modules in those two DSPs are connected directly without a Switch.

I think the most of your setup is correctly. The peculiar results you mentioned in your very first post could be resolved by removing the cache activities inside of the dstBuf checking loop as follows:

    /* EP waits for the data received from RC */
    do {
      unsigned int key;

      /* Disable Interrupts */
      key = _disable_interrupts();

      /* Cleanup the prefetch buffer also. */
      CSL_XMC_invalidatePrefetchBuffer();

      //CACHE_invL1d ((void *)dstBuf, PCIE_EXAMPLE_DSTBUF_BYTES, CACHE_FENCE_WAIT);
      //CACHE_invL2 ((void *)dstBuf, PCIE_EXAMPLE_DSTBUF_BYTES, CACHE_FENCE_WAIT);

      /* Reenable Interrupts. */
      _restore_interrupts(key);

    } while(dstBuf[PCIE_BUFSIZE_APP] != PCIE_EXAMPLE_BUF_FULL);

I think CSL_XMC_invalidatePrefetchBuffer() could be removed as well. I do not how you allocate the dstBuf in your EP source code. By default (in my testing project), dstBuf has been allocated to L2 SRAM. The L1D cache and PCIe master port could keep coherent in L2 SRAM. We could worry about cache coherency later if dstBuf is allocated to external memory like DDR. For the debugging purpose of PCIe issue here, we could comment them out for now.

And you could also use PCIE_BUFSIZE_APP instead of PCIE_BUFSIZE_TEST in the EP code to let RC complete the loopback data check correctly (I think RC checks PCIE_BUFSIZE_APP size). But it is minor.

    pcieBase = (uint32_t*) LOCAL_OB_MEMORY_ADDR_BGPP;

    //for (i=0; i<PCIE_BUFSIZE_TEST; i++)
    for (i=0; i<PCIE_BUFSIZE_APP; i++)
    {
       pcieBase[i] = dstBuf[i];
    }

I tested the EP side up to Read 1 section since I do not have Switch or FPGA in the setup.

After those two changes, I could see the transfers between RC and EP happened correctly. RC dstBuf receives the data from EP and EP could read the data from RC as well.

So could you please bypass the Switch and connect the RC and EP directly to see the if PCIe setup is correct in your application considering the modifications mentioned above?

If the peer-to-peer setup is confirmed to be working, then the issue could be the Switch configuration.

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

More Info:

We have found a post on a similar problem on different vendors products, It dealt with programming the base and limit registers for the Root Complex (RC). In our design we have programmed to the values shown for addresses 0x51801020 - 0x5180102c below. You should also notice that the BAR0 is set to 0x80000000 and BAR1 is set to 0x90000000. I am assuming that any address in the range of 0 to 7fffffff will be passed on to the next bus and more importantly any address outside this range will be accepted by the RC for completion processing. Does this seem correct to you?

-> d 0x51801000

NOTE: memory values are displayed in hexadecimal.

0x51801000: 8888104c 00100006 00000001 00010000 *L...............*

0x51801010: 80000000 90000000 00040000 00000000 *................*

0x51801020: 7ff00000 7ff00000 00000000 00000000 *................*

I am also attaching a zip that includes exports of the captured analyzer data fro both the DSP (EP) and GPP (RC) sides of the switch. In these you will notice ther is no completion for the DSP initiated reads or writes indicated by req ID of 02 00.

6428.04042012.zip

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

I think the RC setup seems fine. The PCIe addresses targeted at RC (0x80000000 or 0x90000000) is out of the range of the base/limit of memory space.

So are you able to test the applications again with bypassing the switch in your setup as mentioned before please? Do you still observe anything wrong please?

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

Steven,

Unfortunately, we do not have an option to bypass the switch. If you can send us adapter for two 6678s we could try it.

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

Steven,

Have you had a chance to look at the analyzer data I sent you?

On th GPP side, you will see the correct transaction requests getting to the RC (GPP), you will also see there are no completions for these requests. To us it looks like something in the RC configuration is not allowing the completion of the transaction requests. The addresses appear to me to match my BAR and address translation setups.

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

Steven,

In the analyzer data I also captured some writes and reads in to the RC application register space through BAR0. I was attempting to write and read the GPR0 - GPR4 registers. There is still no completion.

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

The addresses are at 0x8000070 - 0x8000007c.

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

The RC configuration in the attachment of RC registers dump In your previous post (7245.RC_ConfigPreError.txt) shows something interesting.

CFG_SETUP (0x8) = 0x01040100 -- Could you double check why the RC bus number = 4 and device number =1 in your setup please? I think RC is on the highest bus (bus number=0) in the system.

BUSNUM (0x1018) = 0x00040000 -- Highest bus number on downstream interface = 4. Please check if it is also true for your system.

BAR0 (0x1010) = 0x0 -- It is not set as 0x80000000

I am not sure how the switch is configured in your system but it could be a place to investigate since the switch may not route the packets correctly to RC or EP if ID routing (Bus/Device numbers will matter) is used for memory transaction in your PCIe system.

Sincerely,

Steven

0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

Steven,

CFG_SETUP is used for seting up outbound configuration messages, it does not affect the requestor ID of the device. It hold the last setup used for bus enumeration.I am attaching file for reference:

5342.04062012.zip

We have made some progress since my last update, earlier we could not write into the GPR registers in the RC’s PCIESS, we can now. The difference is I removed the code writing into the memory space and allowed the Register write code to execute first. This works and is captured in “GPP_side_DspRegWrites.csv”. It does not work if the writes follow the writes into the BAR1 space captured in “GPP_side_DspMemWrites.csv”. Examination of the captured data shows that the memory writes and read to 0x900000xx are acked but there are no completion packets for the reads. Examination of address 0xc0000000 in the RC verifies that no writes were successful.

We now believe that there may be some missing piece to configure the PCIe to write into the DDR3 memory at 0xc0000000. I would like you to forward this part of the problem to some Integra expert for review. A further complication is that we are using VxWorks for the MMU setup. WE believe we have it correct but will try to verify with Wind River independently.

We are also to do memory reads & writes into the FPGA EP on port 3 of the switch.

To summarize we can read and write to any EP through the switch from the GPP RC. We can read and write into the FPGA EP form the DSP EP. We cannot read or write into memory space BAR1 on the GPP RC from the DSP. WE can however read and write the GPR registers on the RC PCIESS. The DSP writes to address 0x90000000 for memory and 0x80000000 for the registers (BAR0).

Here is a dump of the inbound translation registers:

-> d 0x51801000,50,4 BAR0 & BAr1 dump

NOTE: memory values are displayed in hexadecimal.

0x51801000: 8888104c 00100007 00000001 00010000 *L...............*

0x51801010: 80000000 90000000 00050100 00000000 *................*

0x51801020: 7ff00000 7ff00000 00000000 00000000 *................*

0x51801030: 00000000 00000040 00000000 000001ff *....@...........*

0x51801040: 00035001 00000000 00000000 00000000 *.P..............*

0x51801050: 00807005 00000000 00000000 00000000 *.p..............*

0x51801060: 00000000 00000000 00000000 00000000 *................*

0x51801070: 00420010 00008001 0001281f 00135422 *..B......(.."T..*

0x51801080: 30220008 00000040 004003c0 00000000 *.."0@.....@.....*

0x51801090: 00000000 0000001f 00000000 00000000 *................*

0x518010a0: 00000002 00000000 00000000 00000000 *................*

0x518010b0: 00000000 00000000 00000000 00000000 *................*

0x518010c0: 00000000 00000000 *................*

-> d 0x51800300 IB_BAR0 dump

NOTE: memory values are displayed in hexadecimal.

0x51800300: 00000001 90000000 00000000 c0000000 *................*

0x51800310: 00000000 00000000 00000000 00000000

Thanks alot for your support.

0 Mark Swick over 13 years ago in reply to Mark Swick

Intellectual 565 points

Is there a way to trnfer this to the Integra Specific forum?