• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 645 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How to synchronise stream - blocks in data I/O

Thomas Brandner
Prodigy 20 points

Hi all,

I use the DSP/BIOS AIC23 Codec Device Driver for the TMS320C6713 DSK  (SPRA677)  brought by TI to access the Audio Codec AIC32 in the development board DSK6713 via input and output streams.

I see no way of using SIO_put / SIO_get or SIO_issue/ SIO_reclaim so that the ADC and the DAC of the codec start reading(writing) into a new buffer at the same time. Is there another possibility to recognise the start of "useful data"  when reading buffers from the input stream, where "useful" means data that is coming from the input stream (from the ADC of the codec) as response to a previously sent a buffer to the output stream?

Regards,

  • 0
    TI__Mastermind 20480 points

    Hi Thomas,

    There is no "true" reading and writing operations to happen at the same time.

    What you can do however is to double-buffer (prime) the SIO buffer with some dummy data (such as 0's) so that you're eliminating the need for the reader to pend on the writer. In other words, you're avoiding context switching delays (except of interrupts) with the reader because it always has data to process while the writer is writing to a separate buffer.

    Take a look at example 7.3.4 Stream I/O using the Issue/Reclaim Model in the DSP/BIOS User's Guide.

  • 0 in reply to Tom Kopriva
    Prodigy 20 points

    Thank you Tom for your answer!

    Well it´s clear that without the priming you mentioned, the reading from the input Stream has to happen "one buffer later" than the writing to the output stream.

    What i don´t see from the documentation of the driver is the following: The (bidirectional) McBSP1 that is used to communicate with the Codec has to start delivering data at some point in time. So the ADC and the DAC of the codec should start working on data at the same time and therefore, the first "useful" input buffer gets fully filled at the very same time the first output Stream buffer gets empty.

    But somehow this seems not to be the case and there is always some offset of "useful" data when comparing input and output stream buffers. What am i missing here?

    I will have a look at the issue/reclaim example you posted, nevertheless the question above stays in my focus ;-)

    Thanks and kind regards,

    Thomas

  • 0 in reply to Thomas Brandner
    TI__Mastermind 20480 points

    Hi Thomas,

    I can't answer this question unfortunately, but I'll forward this thread to the folks who can help you with this.

  • 0 in reply to Tom Kopriva
    TI__Expert 7290 points

    Hi Thomas,

    If you are using the codec in Master mode, then, the bit clock and the sample frequency will be derived from the codec. So, on the occurrence of the sample frequency, the data will be fetched and then transferred (by EDMA from FIFO) to the already primed buffers in McBSP driver.(In case of receive)

    In case of transmit, the EDMA will copy the data to the FIFO and then on the occurrence of the sample frequency, the data will be moved out. As and when the FIFO is emptied or it goes below the threshold value, the EDMA continues to transfer the remaining data.

    So, in summary, the "useful data" can be read or transmitted out on the occurrence of the sample frequency.

    By any chance, if there is a delay in generation of sample frequency and the "useful" data, then there might be a chance of reading the invalid data!!

    Regards,

    Sandeep K