Hi, I need some clarifications on how TSC_ADC_SS works.
Which is the size of FIFOs?
In figure 12-1 of TRM it seems 64 x 16 bit. I suppose that 12 bits are the sampled value and other 4 bits are for the id tag, therefore max 64 samples. But it happens that when I read FIFO0COUNT sometimes I get values grater than 64: how can it be? I've just configured a single step in sw-continuous mode to sample AIN0.
And what does happen when FIFO is full? Is the oldest value discarded and replaced by new sample?
I've set the out-of-range check in stepconfig, a max value in ADCRANGE register and enabled out-of-range IRQ. In the ISR, to get the value that causes the interrupt, do I have to read all the samples in the FIFO0 till the last one? Does the FIFO0DATA register work in a clear-on-read manner?
In the TRM I've found a little bit of confusion between concepts of "step" and "channel": "There are 16 programmable Step Configuration registers which are used by the sequencer to control which switches to turn on or off (inputs to the AFE), which channel to sample, and which mode to use". With "channel" do you mean the input (AIN0, AIN1, etc)? But the ID in FIFO0DATA registers seems to refer to the step more than the channel/input, even if it is described as "Optional ID tag of channel that captured the data".
Best regards,
Max