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AM1808 Timer triggers PRD34 interrupt when PRD34 disabled.

Other Parts Discussed in Thread: AM1808

Hi everyone,

I have a question about the timer of the AM1808.

I am using Timer2 in the dual 32-bit timers unchained mode, with the "Plus" features disabled.
Timer1:2 is setup for continuous operation, PRD12 = 0x00003a97
Timer3:4 is setup for continuous operation, PRD34 = 0xffffffff
Only PRDINTEN12 is set in INTCTLSTAT
An internal clock frequency of 150MHz is used.

My goal is to have Timer1:2 interrupt the ARM CPU every 100us.
Timer3:4 is provided as a commodity to the application software for time-stamping,etc.

What is puzzling me is that Timer3:4 appears to trigger an event to the interrupt controller when it reloads, even if PRDINTEN34 is not set in INTCTLSTAT. I was assuming that only the period event of Timer1:2 part would trigger an interrupt as it is the only event enabled in Timer2.

Everything else is behaving normally: The interrupt handler is entered every 100us, with PRDINTSTAT12 set in the INTCTLSTAT reg of Timer2.
The only thing I do not understand is that every 28 seconds (the period of Timer3:4) the interrupt handler is entered, with PRDINTSTAT12 cleared and PRDINTSTAT34 set.

The interrupts for timer 2, Timer64P2 Combined Interrupt (TINT12 and TINT34), is mapped on channel 0 of the interrupt controller.
It is the only source for the FIQ interrupt.

Is this the expected behavior of the timer, a known erratum, or I simply misconfigured the timer ?

Below is a dump of the registers of Timer2 in operation.

0x01f0c000:  4472020c 00000000 00000000 00000000  *..rD............*
0x01f0c010:  00003949 76fc4a8f 00003a97 ffffffff  *I9...J.v.:......*
0x01f0c020:  00800088 00000007 00000000 00000290  *................*
0x01f0c030:  00000000 00003a97 ffffffff 00000000  *.....:..........*
0x01f0c040:  00000000 00000001 00000000 00000000  *................*
0x01f0c050:  00000000 00000000 00000000 00000000  *................*
0x01f0c060:  ffffffff ffffffff ffffffff ffffffff  *................*
0x01f0c070:  ffffffff ffffffff ffffffff ffffffff  *................*

Regards,

Michel