Hi,
I'm new to 5502 and I'm working on a ADC / DAC daugtherboard to be mounted on TI 5502 EVM for proof of concept of a new hardware device, and I'd like keep the daughterboard simple as possible for timing issues.
I' d like to connect gluelessly ADS8319 ADC and DAC8830 DAC to McBSP 0 & 1 ports of 5502 configured as SPI master and, this is the main point, I'd like the McBSP entirely manage automatically the input and output data transfer with its internal clock and sync generation together with DMA but it seems to me that this is not possible.
The ADS8319 and DAC8830, as other similar devices, use the SPI CS (McBsp's FS) to start the conversion and need gaps between frames with CS high during the conversion.
I see that in the McBsp SPI mode frame-sync pulse width and frame-sync period of the sample rate generator are not programmable and it is not possible to set a desired delay between the falling edges of consecutive FS, and consequently it is not possible to define gaps between frames.
Moreover FSGM bit must be set at 0, and as far I understand a frame sync pulse will be generated only when a word of data is written, and not automatically by the McBsp.
So I guess that:
- in SPI mode it not possible to have the data transfer fully managed by the McBsp and DMA, and I should manage the data transfer using timers or external signals that launch interrupts + code or DMA events.
- as a consequence neither make sense to ask the McBsp to automatically geneate frames with programmable gaps.
Can you help me and confirm this or correct me if I'm wrong? I read the documentation (spru592e) but I may have misunderstood something and it is important for me to be sure.
If I'm wrong, as I hope, any hint to understand how to do what I need is appreciated.
If I'm right any suggestion about how to manage at better the data transfer with less CPU effort is appreciated too.
Thank you for your help.
Alberto
