output 25Mhz on pin CLKOUT1

CLKOUT1 is a buffered output of the master oscillator.  If you are using a 24MHz crystal, you will get a 24MHz clock output from XDMA_EVENT_INT0 pin configured to operate as CLKOUT1 when SYSBOOT[5] is pulled high before the rising edge of PRWONRSTn.

You may be able to configure CLKOUT2 to get a 25MHz clock when using a 24MHz crystal.  The XDMA_EVENT_INT1 pin can be configured to output CLKOUT2 which can be sourced from several internal clock sources.  Refer to the CLKOUT Signals section of the AM335x TRM for more details of configuring this mode of operation.

SYSBOOT[15:14] are only read by boot ROM code to indicate the clock frequency of the master oscillator.

Regards,
Paul

Hi,

Thanks for reply.

i have write a code to configure the CLKOUT2 to output 25Mhz. i put my coding in  

ti-sdk-am335x-evm-05.03.00.00/board-support/u-boot-2011.09-psp04.06.00.02/board/ti/am335x/evm.c

so that my code would be executed in u-boot.

in u-boot, i'm sure my code is being executed but nothing come out from CLKOUT2,  but once i boot my kernel, the CLKOUT2 will output 25Mhz.

i want CLKOUT2 output 25Mhz in u-boot, not in kernel.

What i have miss? like interface clock of PCRM or other thing else?

Thanks,

Keldy

Hi Keldy,

What values are you setting in "CM_CLKOUT_CTRL and control_status" registers?

Are you touching any other registers?

Regards

AnilKumar

Hi,

CM_CLKOUT_CTRL = 0x9c;

i didn't touch the control_status register.

my code is as following:

 u32 val;
 val = __raw_readl(CONF_XDMA_EVENT_INTR1);            //pin_mux
 __raw_writel(val | 0x3, CONF_XDMA_EVENT_INTR1);
 
 val = __raw_readl(CM_CLKSEL_DPLL_DISP);
 __raw_writel(val & (~(1 << 23)), CM_CLKSEL_DPLL_DISP);

 __raw_writel(0x0, CLKSEL_LCDC_PIXEL_CLK);

 __raw_writel(0x4, CM_CLKMODE_DPLL_DISP);

 val = __raw_readl(CM_CLKMODE_DPLL_DISP);
 __raw_writel(val | (1 << 15), CM_CLKMODE_DPLL_DISP);

 while((__raw_readl(CM_IDLEST_DPLL_DISP)) != 0x00000100);

 __raw_writel(0x6418, CM_CLKSEL_DPLL_DISP);

 val = __raw_readl(CM_DIV_M2_DPLL_DISP);
 __raw_writel(val | (1 << 8), CM_DIV_M2_DPLL_DISP);
 val = __raw_readl(CM_DIV_M2_DPLL_DISP);
 __raw_writel(val | (1 << 0), CM_DIV_M2_DPLL_DISP);
 val = __raw_readl(CM_DIV_M2_DPLL_DISP);
 __raw_writel(val & (~(1 << 2)), CM_DIV_M2_DPLL_DISP);
 val = __raw_readl(CM_DIV_M2_DPLL_DISP);
 __raw_writel(val & (~(1 << 4)), CM_DIV_M2_DPLL_DISP);

 val = __raw_readl(CM_CLKMODE_DPLL_DISP);
 __raw_writel(val | 0x7, CM_CLKMODE_DPLL_DISP);

 while((__raw_readl(CM_IDLEST_DPLL_DISP)) != 0x1);

 __raw_writel(0x9c, CM_CLKOUT_CTRL);

Thanks,

Keldy

Hi Keldy,

1. __raw_writel(0x6418, CM_CLKSEL_DPLL_DISP); ==> this will result CLKOUT of DISP PLL to 96MHz

2. Finally what value you are trying to set in this register?

 val = __raw_readl(CM_DIV_M2_DPLL_DISP);
 __raw_writel(val | (1 << 8), CM_DIV_M2_DPLL_DISP);
 val = __raw_readl(CM_DIV_M2_DPLL_DISP);
 __raw_writel(val | (1 << 0), CM_DIV_M2_DPLL_DISP);
 val = __raw_readl(CM_DIV_M2_DPLL_DISP);
 __raw_writel(val & (~(1 << 2)), CM_DIV_M2_DPLL_DISP);
 val = __raw_readl(CM_DIV_M2_DPLL_DISP);
 __raw_writel(val & (~(1 << 4)), CM_DIV_M2_DPLL_DISP);

3. What frequency you are seeing at CLKOUT2 from your current settings?

Regards

AnilKumar

Please mark this Forum post as answered via the Verify Answer button below if it helps answer your question.  Thanks!

Hi,

sorry for my mistake for no. 1, should be  __raw_writel(0x6417, CM_CLKSEL_DPLL_DISP); (100Mhz)

for question 2, i want to set post div to 1,  CM_DIV_M2_DPLL_DISP. DPLL_CLKOUT_DIV = 1 , and i want to enable clock, CM_DIV_M2_DPLL_DISP.DPLL_CLKOUT_GATE_CTRL = 1.

__raw_writel(0x9c, CM_CLKOUT_CTRL); // (100Mhz / 4 = 25Mhz), CLKOUT2 enable, select Pixel clock

my current CLKOUT2 output now is 25Mhz, but this clock will only available after i boot the kernel, i want this clock to be available in u-boot. What register i have miss to configure?

Thanks & Regards,

Keldy.