DSP TMS320C6678 - Clocking Solution

While the solution you've presented will work you have included a second clock generator that I don't think you need.  The CDCE62005 can't generate 312.5MHz, 100MHz and 66.67MHz but it can generate 250MHz, 100MHz and 66.67MHz.  The clocking requirements for the SRIOSGMIICLKP/N inputs require one of following three supported frequencies; 312.5MHz, 250MHz or 156.25MHz.  312.5MHz was used on the EVM but you can eliminate the CDCE62002 from your design if you use the CDCE62005 to generate 250MHz and connect that directly to the C6678.  Make sure you terminate you unused clocks as shown in the hardware design guide.  Note that you'll have to pull the PACLKSEL configuration pin low to direct the PA subsystem to use the CORECLK inputs. 

Hi Bill Taboada,

Thank you for your inputs.

As per your inputs, we are planning to provide clocks to DSP from single CDCE62005 as below. 

CORECLK – 100 MHz

SRIOSGMIICLK – 125 MHz (In our system, we will operate SRIO at 1.25 Gbps)

DDR CLK – 66.67 MHz / 80 MHz / 51.65 MHz

 We are planning to operate DDR at three different frequencies 1333 MHz/1600 MHz/ 1033 MHz as required, so the required input clocks are 66.67 MHz / 80 MHz / 51.65 MHz respectively.

 Please confirm whether it is possible to get these frequency sets  from CDCE62005 else provide your suggestion for these.

 Please share if any frequency calculation document or tool is available for CDCE62005.

Thank you.

First let me correct myself.  It's not possible to generate the combination of 250MHz/100MHz/66.67MHz with the CDCE62005.  You can generate all the clocks you need with a single CDCE62005 but you need to use the PLLs inside the C6678 to get the final frequencies.  The CDCE62005 should be programmed to generate 250MHz/100MHz/50MHz for the SRIOSGMIICLK/CORECLK/DDRCLK respectively.  Let me address your post in detail below.

1)  You can't use 125MHz for the SRIOSGMIICLK.  This clock input only support three specific frequencies which are 156.25MHz, 250MHz and 312.5MHz.  The first and last can't be generated along with the 100MHz and the 50MHz so you should use 250MHz for that clock.

2) You don't need to generate separate clocks to use different frequency DDR3 interfaces.  Program the CDCE62005 to generate a 50MHz clock for the DDRCLK input and program the DDR PLL inside the part as follows to get the frequency you need for the DDR3 components you've installed.