We are finishing up layout on the TI Sitara board and having problems with the DDR2 Hyperlynx simulation. Using the Micron MT47H64M16HR x16 DDR2's, -25E speedgrade. This should be plenty good, since we are clocking at 166MHz.
We followed the AM3505 DDR2 layout recommendations in the Datasheet. I am getting some strange behavior in HyperLynx.
The problems are likely with the IBIS model (am35xxzer, sprm504, Version 4.1, May10,2010)
1) When I do an IBIS check, there are several warnings (about 179) relating to non-monotonic signals. The header in the IBIS file says to ignore these... but it does affect my simulation results.
2) The IBIS model does not have any reference to the [DIFF PIN] signals, which makes the simulation choke.I added definitions, but they do not have all the threshold information.
3) The ODT is behavior for the AM3505 is not documented anywhere... I assume ODT is inside the part, as it isimportant for read cycles. The IBIS model does not have ODT characteristics built in, so I can't simulate a DDR2 read cycle.
Does TI have an updated IBIS model that has DIFF PINS, ODT characteristics ?
Is there someone at TI that has setup HyperLynx simulation for DDR2?