starterWare startup.c for AM335X

brad badke

Maybe somebody could fill me in a little bit about startup.c in starterWare? Like what the exact ARM instructions are in those first 8 lines of the table? I will be doing something similar in my boot loader so I would like some clarification. I am also a bit confused about AM335X_VECTOR_BASE. I thought AM335X_VECTOR_BASE should be 0x4030CE20 based on spruh73c.pdf chapter 26 on initialization.

//Code from startup.c

const unsigned int AM335X_VECTOR_BASE = 0x4030FC00;

static unsigned int const vecTbl[14]=
{
    0xE59FF018,                     //ldr ARM instruction
    0xE59FF018,                     //ldr ARM instruction
    0xE59FF018,                     //ldr ARM instruction
    0xE59FF018,                     //ldr ARM instruction
    0xE59FF014,                     //
    0xE24FF008,                     //
    0xE59FF010,                     //
    0xE59FF010,                     //
    (unsigned int)Entry,             //Entry is in bl_init.s --- basically the reset handler
    (unsigned int)UndefInstHandler, //Undefined (bpb) (same as AbortHandler for some reason)
    (unsigned int)SVCHandler,        //SWI or software interrupt (bpb)
    (unsigned int)AbortHandler,      //Why not separate data and prefetch abort??? (bpb)
    (unsigned int)IRQHandler,
    (unsigned int)FIQHandler
};

over 13 years ago

0 Sujith KV over 13 years ago

TI__Intellectual 2525 points

Hi,

In the vector table, vectTbl, as you pointed out, we define the opcodes for LDR instructions to load program counter with the addresses of individual exception handlers. Anyway, StarterWare leaves it to the implementer to decide on separate data abort/prefetch abort if it is required. StarterWare currently does not perform any action upon reception of an abort. So as part of your application, you can definitely have separate data/prefetch abort handlers.

As cortexA8 core will permit the exception vector base address to be anywhere in the memory map, AM335X_VECTOR_BASE is moved to the end (infact very close to the end) of OCMC RAM 0x4030FC00. This would allow us to have some more space in OCMC RAM for other purposes, without corrupting the vector table. For example, if we relocate a section of code from DDR to OCMC RAM during run-time, which would reach upto 0x4030D000, your default vector table will get corrupted. To avoid this, we give a little more space in the OCMC RAM . However, if you dont want to use OCMC RAM, you can leave the vector table at 0x4030CE20.

Regards,

Sujith.

0 brad badke over 13 years ago in reply to Sujith KV

Intellectual 760 points

I just used the default location in my OMAP boot code and figured I would do the same with Sitara. But this is a useful option. Thanks.

0xE59FF018 is an ldr

what is 0xE24FF008 ?

0 Sujith KV over 13 years ago in reply to brad badke

TI__Intellectual 2525 points

Hi,

That is the opcode for a while(1), to halt there itself. (SUB PC, PC, #8). There is no handler defined for that location.

Regards,

Sujith.

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starterWare startup.c for AM335X