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Base adress Registers in PCI Express on the C6678

ait el maati younes
Prodigy 210 points

Hello ,

My question is about the base adress registers implemented in your product .

my job is to connect the C6678 (DEvice A as RC ) and a Device B ( as EP) .

So can i know what is the relationship betwenn BARs of device A and the  memory space of  device B ,

Can i say that  they play the same role of pointers in C language  , which  means that they contain the adress of the begining of a contigous memory space in the other device ????

Thank You

  • 0
    Expert 1305 points

    If A is the RC and B is the EP, then you probably want to concern yourself with the BARs of device B.  The EP device can have up to 6 BARs.  The EP sets the size of these BARs to signal to the RC how much of the bus address space the device needs.  The RC will program the address(es) of the EP's BAR(s) to indicate which section(s) of the bus address space the device has been assigned.  How the device responds to reads/writes to these addresses will depend on the device.  For the C6678, you can configure the PCIe peripheral's address translation unit to 'redirect' or 'map' these addresses to L3 addresses of the SOC (which could be DDR, L2, other peripherals, ...).

    Hope that helps a little.

    -Joel

  • 0 in reply to Joel Keller
    TI__Genius 12065 points

    Hi,

    What Joel said is correct. We should setup the BARs in Device B (EP). The BAR is like the memory window on PCIe bus. The RC will send out the PCIe packets with certain PCIe addresses. Those packets will be accepted by EP, which has the BAR setup matching to those PCIe addresses.

    In most of cases, we will also need to setup the Outbound/Inbound address translation in C66x PCIe module to link the internal device memory space to the PCIe data space.Then the RC could write/read data (with the Outbound translation setup on RC) to/from EP internal device memory region (with the help of the BAR/Inbound configuration on EP).

    Please refer to Section 3 in the PCIe applications note for details of the BAR setup and address translation.

    Hope it helps.

    Sincerely,

    Steven

  • 0 in reply to Steven Ji
    Prodigy 210 points

    Thank you very much joel end steaven , you information helped me ,

     

    i wanna just know if there is a CSL module for PCIe , giving me direct access to the devices registers to put in values

     

    thanks

  • 0 in reply to ait el maati younes
    TI__Genius 12065 points

    If you just want to access the PCIe registers and program them directly, you could refer to the CSL PCIe header files to access the registers (such as cslr_pciess_app.h, cslr_pcie_cfg_space_endpoint.h,etc.). But there is no functional layer support in CSL package for PCIe.

    If you need to use PCIe intensively and prefer API support for this module, the PCIe LLD in the MCSDK package will be recommended. It has the documentation and example for API usage. Please refer to the PCIe LLD folder "\ti\pdk_C6678_1_0_0_17\packages\ti\drv\pcie".

    Sincerely,

    Steven