Hi
To support our board which has a 26 MHz oscillator instead the 24 MHz of the EVM, I've just modified the PLLs N-divisors value in SPL/U-Boot code in arch/arm/include/asm/arch-ti81xx/clocks_am335x.h: 25 instead of 23. Is it enough or do I need further changes?
I'm asking this because everything seemed ok with SDK 5.03 Kernel (PSP 04.06.00.03), which boots with these logs...
[ 0.000000] OMAP clockevent source: GPTIMER1 at 26000000 Hz
[ 0.000000] OMAP clocksource: GPTIMER2 at 26000000 Hz
[ 0.000000] sched_clock: 32 bits at 26MHz, resolution 38ns, wraps every 165191ms
...but after I moved to PSP 04.06.00.06, kernel boots detecting wrong frequency:
[ 0.000000] OMAP clockevent source: GPTIMER1 at 24000000 Hz
[ 0.000000] OMAP clocksource: GPTIMER2 at 24000000 Hz
I had a quick look at kernel code, file arch/arm/mach-omap2/clock33xx_data.c: in PSP 04.06.00.06 it seems missing something already present in PSP 04.06.00.03 and now present also in git staging tree version, that I think can be related to the issue:
PSP 04.06.00.06:
static struct clk sys_clkin_ck = {
.name = "sys_clkin_ck",
.rate = 24000000,
.ops = &clkops_null,
};
PSP 04.06.00.03 and staging branch:
/* Oscillator clock */
/* 19.2, 24, 25 or 26 MHz */
static const struct clksel sys_clkin_sel[] = {
{ .parent = &virt_19_2m_ck, .rates = div_1_0_rates },
{ .parent = &virt_24m_ck, .rates = div_1_1_rates },
{ .parent = &virt_25m_ck, .rates = div_1_2_rates },
{ .parent = &virt_26m_ck, .rates = div_1_3_rates },
{ .parent = NULL },
};
/* sys_clk_in */
static struct clk sys_clkin_ck = {
.name = "sys_clkin_ck",
.parent = &virt_24m_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = AM33XX_CONTROL_STATUS,
.clksel_mask = AM33XX_SYSBOOT1,
.clksel = sys_clkin_sel,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
};
Any suggestion to understand and solve the issue?
Is PSP 04.06.00.06 missing some other specific features already available in previous PSP?
Thanks. Regards,
Max
