Hi again!
We have developed a Centaurus (8148) module with 4x256 MB (2 at each EMIF) with 1 CS (16-Bit data each=32-Bit total). We operate it with a CLK of 400 MHz. Currently we
want to access and configure the DDR3 registers in order to access it at Low-Level C.
We use the following .gel file:
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Project : TIDM814x
File : TIDM814x_ddr.gel
Purpose : TIDM814x DDR initialization for DDR2/3 interface
Platform : TI DM814x EVM
Version Hystory
---------------
Version Date Who Description
------- ----------- ------ -----------
Ver7.0 27-Sept-2011 raj@ti.com DDR2/DDR3 Configurations for different speeds
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
#define PRCM_BASE_ADDR 0x48180000
#define DMM_BASE_ADDR 0x4E000000
#define EMIF4_0_CFG_BASE_ADDR 0x4C000000
#define EMIF4_1_CFG_BASE_ADDR 0x4D000000
#define GPMC_MEM_BASE_ADDR 0x02000000
#define DDR_MEM_BASE_ADDR 0x80000000
#define DUCATI_BASE_ADDR 0x55020000
#define DUCATI_MMU_CFG 0x55080000
#define CTRL_MODULE_BASE_ADDR 0x48140000
#define GEM_L2RAM_BASE_ADDR 0x40800000
/* Control Module*/
#define CM_CTRL_CLKCTRL 0x481815c4
#define DSPBOOTADDR (CTRL_MODULE_BASE_ADDR + 0x0048)
#define DSPMEM_SLEEP (CTRL_MODULE_BASE_ADDR + 0x0650)
#define CM_ALWON_L3_SLOW_CLKSTCTRL (PRCM_BASE_ADDR + 0x1400)
/*UART*/
#define CM_ALWON_UART_0_CLKCTRL (PRCM_BASE_ADDR + 0x1550)
#define CM_ALWON_UART_1_CLKCTRL (PRCM_BASE_ADDR + 0x1554)
#define CM_ALWON_UART_2_CLKCTRL (PRCM_BASE_ADDR + 0x1558)
#define CM_DEFAULT_DUCATI_CLKSTCTRL (PRCM_BASE_ADDR + 0x0518)
#define CM_DEFAULT_DUCATI_CLKCTRL (PRCM_BASE_ADDR + 0x0574)
#define RM_DEFAULT_RSTCTRL (PRCM_BASE_ADDR + 0x0B10)
#define RM_DEFAULT_RSTST (PRCM_BASE_ADDR + 0x0B14)
#define CM_ALWON_OCMC_0_CLKSTCTRL (PRCM_BASE_ADDR + 0x1414)
#define CM_ALWON_OCMC_0_CLKCTRL (PRCM_BASE_ADDR + 0x15B4)
#define CM_ALWON_GPMC_CLKCTRL (PRCM_BASE_ADDR + 0x15D0)
#define CM_ALWON_L3_SLOW_CLKSTCTRL (PRCM_BASE_ADDR + 0x1400)
#define OCMC0RAM_BASE_ADDR 0x40300000
#define OCMC1RAM_BASE_ADDR 0x40400000
#define CM_DEFAULT_L3_FAST_CLKSTCTRL (PRCM_BASE_ADDR + 0x0508)
#define CM_DEFAULT_EMIF_0_CLKCTRL (PRCM_BASE_ADDR + 0x0520)
#define CM_DEFAULT_EMIF_1_CLKCTRL (PRCM_BASE_ADDR + 0x0524)
#define CM_DEFAULT_DMM_CLKCTRL (PRCM_BASE_ADDR + 0x0528)
#define CM_DEFAULT_FW_CLKCTRL (PRCM_BASE_ADDR + 0x052C)
#define DDR0_PHY_BASE_ADDR 0x47C0C400
#define DDR1_PHY_BASE_ADDR 0x47C0C800
#define DDR0_IO_CTRL 0x48140E04
#define DDR1_IO_CTRL 0x48140E08
#define VTP0_CTRL_REG 0x48140E0C
#define VTP1_CTRL_REG 0x48140E10
#define EMIF4_0_CFG_BASE_ADDR 0x4C000000
#define EMIF4_1_CFG_BASE_ADDR 0x4D000000
#define DMM_BASE_ADDR 0x4E000000
//-DMM & EMIF4 MMR Declaration
#define DMM_LISA_MAP__0 (DMM_BASE_ADDR + 0x40)
#define DMM_LISA_MAP__1 (DMM_BASE_ADDR + 0x44)
#define DMM_LISA_MAP__2 (DMM_BASE_ADDR + 0x48)
#define DMM_LISA_MAP__3 (DMM_BASE_ADDR + 0x4C)
#define DMM_PAT_BASE_ADDR (DMM_BASE_ADDR + 0x460)
#define EMIF4_0_SDRAM_CONFIG (EMIF4_0_CFG_BASE_ADDR + 0x08)
#define EMIF4_0_SDRAM_CONFIG2 (EMIF4_0_CFG_BASE_ADDR + 0x0C)
#define EMIF4_0_SDRAM_REF_CTRL (EMIF4_0_CFG_BASE_ADDR + 0x10)
#define EMIF4_0_SDRAM_REF_CTRL_SHADOW (EMIF4_0_CFG_BASE_ADDR + 0x14)
#define EMIF4_0_SDRAM_TIM_1 (EMIF4_0_CFG_BASE_ADDR + 0x18)
#define EMIF4_0_SDRAM_TIM_1_SHADOW (EMIF4_0_CFG_BASE_ADDR + 0x1C)
#define EMIF4_0_SDRAM_TIM_2 (EMIF4_0_CFG_BASE_ADDR + 0x20)
#define EMIF4_0_SDRAM_TIM_2_SHADOW (EMIF4_0_CFG_BASE_ADDR + 0x24)
#define EMIF4_0_SDRAM_TIM_3 (EMIF4_0_CFG_BASE_ADDR + 0x28)
#define EMIF4_0_SDRAM_TIM_3_SHADOW (EMIF4_0_CFG_BASE_ADDR + 0x2C)
#define EMIF4_0_DDR_PHY_CTRL_1 (EMIF4_0_CFG_BASE_ADDR + 0xE4)
#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW (EMIF4_0_CFG_BASE_ADDR + 0xE8)
#define EMIF4_0_SDRAM_ZQCR (EMIF4_0_CFG_BASE_ADDR + 0xC8)
#define EMIF4_0_RDWR_LVL_RMP_CTRL (EMIF4_0_CFG_BASE_ADDR + 0xD8)
#define EMIF4_0_RDWR_LVL_CTRL (EMIF4_0_CFG_BASE_ADDR + 0xDC)
#define EMIF4_1_SDRAM_CONFIG (EMIF4_1_CFG_BASE_ADDR + 0x08)
#define EMIF4_1_SDRAM_CONFIG2 (EMIF4_1_CFG_BASE_ADDR + 0x0C)
#define EMIF4_1_SDRAM_REF_CTRL (EMIF4_1_CFG_BASE_ADDR + 0x10)
#define EMIF4_1_SDRAM_REF_CTRL_SHADOW (EMIF4_1_CFG_BASE_ADDR + 0x14)
#define EMIF4_1_SDRAM_TIM_1 (EMIF4_1_CFG_BASE_ADDR + 0x18)
#define EMIF4_1_SDRAM_TIM_1_SHADOW (EMIF4_1_CFG_BASE_ADDR + 0x1C)
#define EMIF4_1_SDRAM_TIM_2 (EMIF4_1_CFG_BASE_ADDR + 0x20)
#define EMIF4_1_SDRAM_TIM_2_SHADOW (EMIF4_1_CFG_BASE_ADDR + 0x24)
#define EMIF4_1_SDRAM_TIM_3 (EMIF4_1_CFG_BASE_ADDR + 0x28)
#define EMIF4_1_SDRAM_TIM_3_SHADOW (EMIF4_1_CFG_BASE_ADDR + 0x2C)
#define EMIF4_1_DDR_PHY_CTRL_1 (EMIF4_1_CFG_BASE_ADDR + 0xE4)
#define EMIF4_1_DDR_PHY_CTRL_1_SHADOW (EMIF4_1_CFG_BASE_ADDR + 0xE8)
#define EMIF4_1_SDRAM_ZQCR (EMIF4_1_CFG_BASE_ADDR + 0xC8)
#define EMIF4_1_RDWR_LVL_RMP_CTRL (EMIF4_1_CFG_BASE_ADDR + 0xD8)
#define EMIF4_1_RDWR_LVL_CTRL (EMIF4_1_CFG_BASE_ADDR + 0xDC)
//- DDR0 Phy MMRs
#define CMD0_REG_PHY0_CTRL_SLAVE_RATIO_0 (0x01C + DDR0_PHY_BASE_ADDR)
#define CMD0_REG_PHY0_DLL_LOCK_DIFF_0 (0x028 + DDR0_PHY_BASE_ADDR)
#define CMD0_REG_PHY0_INVERT_CLKOUT_0 (0x02C + DDR0_PHY_BASE_ADDR)
#define CMD1_REG_PHY0_CTRL_SLAVE_RATIO_0 (0x050 + DDR0_PHY_BASE_ADDR)
#define CMD1_REG_PHY0_DLL_LOCK_DIFF_0 (0x05C + DDR0_PHY_BASE_ADDR)
#define CMD1_REG_PHY0_INVERT_CLKOUT_0 (0x060 + DDR0_PHY_BASE_ADDR)
#define CMD2_REG_PHY0_CTRL_SLAVE_RATIO_0 (0x084 + DDR0_PHY_BASE_ADDR)
#define CMD2_REG_PHY0_DLL_LOCK_DIFF_0 (0x090 + DDR0_PHY_BASE_ADDR)
#define CMD2_REG_PHY0_INVERT_CLKOUT_0 (0x094 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_RD_DQS_SLAVE_RATIO_0 (0x0C8 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_WR_DQS_SLAVE_RATIO_0 (0x0DC + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_WRLVL_INIT_RATIO_0 (0x0F0 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_WRLVL_INIT_MODE_0 (0x0F8 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_GATELVL_INIT_RATIO_0 (0x0FC + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_GATELVL_INIT_MODE_0 (0x104 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_RD_DQS_GATE_SLAVE_RATIO_0 (0x108 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_WR_DATA_SLAVE_RATIO_0 (0x120 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_USE_RANK0_DELAYS (0x134 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_DLL_LOCK_DIFF_0 (0x138 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_RD_DQS_SLAVE_RATIO_0 (0x16C + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_WR_DQS_SLAVE_RATIO_0 (0x180 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_WRLVL_INIT_RATIO_0 (0x194 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_WRLVL_INIT_MODE_0 (0x19C + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_GATELVL_INIT_RATIO_0 (0x1A0 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_GATELVL_INIT_MODE_0 (0x1A8 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_RD_DQS_GATE_SLAVE_RATIO_0 (0x1AC + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_WR_DATA_SLAVE_RATIO_0 (0x1C4 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_USE_RANK0_DELAYS (0x1D8 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_DLL_LOCK_DIFF_0 (0x1DC + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_RD_DQS_SLAVE_RATIO_0 (0x210 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_WR_DQS_SLAVE_RATIO_0 (0x224 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_WRLVL_INIT_RATIO_0 (0x238 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_WRLVL_INIT_MODE_0 (0x240 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_GATELVL_INIT_RATIO_0 (0x244 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_GATELVL_INIT_MODE_0 (0x24C + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_RD_DQS_GATE_SLAVE_RATIO_0 (0x250 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_WR_DATA_SLAVE_RATIO_0 (0x268 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_USE_RANK0_DELAYS (0x27C + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_DLL_LOCK_DIFF_0 (0x280 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_RD_DQS_SLAVE_RATIO_0 (0x2B4 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_WR_DQS_SLAVE_RATIO_0 (0x2C8 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_WRLVL_INIT_RATIO_0 (0x2DC + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_WRLVL_INIT_MODE_0 (0x2E4 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_GATELVL_INIT_RATIO_0 (0x2E8 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_GATELVL_INIT_MODE_0 (0x2F0 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_RD_DQS_GATE_SLAVE_RATIO_0 (0x2F4 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_WR_DATA_SLAVE_RATIO_0 (0x30C + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_USE_RANK0_DELAYS (0x320 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_DLL_LOCK_DIFF_0 (0x324 + DDR0_PHY_BASE_ADDR)
//- DDR1 Phy MMRs
#define CMD0_REG_PHY1_CTRL_SLAVE_RATIO_0 (0x01C + DDR1_PHY_BASE_ADDR)
#define CMD0_REG_PHY1_DLL_LOCK_DIFF_0 (0x028 + DDR1_PHY_BASE_ADDR)
#define CMD0_REG_PHY1_INVERT_CLKOUT_0 (0x02C + DDR1_PHY_BASE_ADDR)
#define CMD1_REG_PHY1_CTRL_SLAVE_RATIO_0 (0x050 + DDR1_PHY_BASE_ADDR)
#define CMD1_REG_PHY1_DLL_LOCK_DIFF_0 (0x05C + DDR1_PHY_BASE_ADDR)
#define CMD1_REG_PHY1_INVERT_CLKOUT_0 (0x060 + DDR1_PHY_BASE_ADDR)
#define CMD2_REG_PHY1_CTRL_SLAVE_RATIO_0 (0x084 + DDR1_PHY_BASE_ADDR)
#define CMD2_REG_PHY1_DLL_LOCK_DIFF_0 (0x090 + DDR1_PHY_BASE_ADDR)
#define CMD2_REG_PHY1_INVERT_CLKOUT_0 (0x094 + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_RD_DQS_SLAVE_RATIO_0 (0x0C8 + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_WR_DQS_SLAVE_RATIO_0 (0x0DC + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_WRLVL_INIT_RATIO_0 (0x0F0 + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_WRLVL_INIT_MODE_0 (0x0F8 + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_GATELVL_INIT_RATIO_0 (0x0FC + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_GATELVL_INIT_MODE_0 (0x104 + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_RD_DQS_GATE_SLAVE_RATIO_0 (0x108 + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_WR_DATA_SLAVE_RATIO_0 (0x120 + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_USE_RANK0_DELAYS (0x134 + DDR1_PHY_BASE_ADDR)
#define DATA0_REG_PHY1_DLL_LOCK_DIFF_0 (0x138 + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_RD_DQS_SLAVE_RATIO_0 (0x16C + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_WR_DQS_SLAVE_RATIO_0 (0x180 + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_WRLVL_INIT_RATIO_0 (0x194 + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_WRLVL_INIT_MODE_0 (0x19C + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_GATELVL_INIT_RATIO_0 (0x1A0 + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_GATELVL_INIT_MODE_0 (0x1A8 + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_RD_DQS_GATE_SLAVE_RATIO_0 (0x1AC + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_WR_DATA_SLAVE_RATIO_0 (0x1C4 + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_USE_RANK0_DELAYS (0x1D8 + DDR1_PHY_BASE_ADDR)
#define DATA1_REG_PHY1_DLL_LOCK_DIFF_0 (0x1DC + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_RD_DQS_SLAVE_RATIO_0 (0x210 + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_WR_DQS_SLAVE_RATIO_0 (0x224 + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_WRLVL_INIT_RATIO_0 (0x238 + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_WRLVL_INIT_MODE_0 (0x240 + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_GATELVL_INIT_RATIO_0 (0x244 + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_GATELVL_INIT_MODE_0 (0x24C + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_RD_DQS_GATE_SLAVE_RATIO_0 (0x250 + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_WR_DATA_SLAVE_RATIO_0 (0x268 + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_USE_RANK0_DELAYS (0x27C + DDR1_PHY_BASE_ADDR)
#define DATA2_REG_PHY1_DLL_LOCK_DIFF_0 (0x280 + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_RD_DQS_SLAVE_RATIO_0 (0x2B4 + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_WR_DQS_SLAVE_RATIO_0 (0x2C8 + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_WRLVL_INIT_RATIO_0 (0x2DC + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_WRLVL_INIT_MODE_0 (0x2E4 + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_GATELVL_INIT_RATIO_0 (0x2E8 + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_GATELVL_INIT_MODE_0 (0x2F0 + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_RD_DQS_GATE_SLAVE_RATIO_0 (0x2F4 + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_WR_DATA_SLAVE_RATIO_0 (0x30C + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_USE_RANK0_DELAYS (0x320 + DDR1_PHY_BASE_ADDR)
#define DATA3_REG_PHY1_DLL_LOCK_DIFF_0 (0x324 + DDR1_PHY_BASE_ADDR)
#define DATA_MACRO_0 0
#define DATA_MACRO_1 1
#define DATA_MACRO_2 2
#define DATA_MACRO_3 3
#define DDR_PHY0 0
#define DDR_PHY1 1
#define DDR_FREQ 800
//- Common DDR PHY parameters
#define PHY_INVERT_CLKOUT_DEFINE 0
#define DDR3_PHY_INVERT_CLKOUT_ON 1
#define DDR3_PHY_INVERT_CLKOUT_OFF 0
#define PHY_REG_USE_RANK0_DELAY_DEFINE 0
#define mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE 1
#define PHY_DLL_LOCK_DIFF_DEFINE 0x4
#define PHY_CMD0_DLL_LOCK_DIFF_DEFINE 0x4
#define PHY_GATELVL_INIT_CS0_DEFINE 0x0
#define PHY_WRLVL_INIT_CS0_DEFINE 0x0
#define PHY_GATELVL_INIT_CS1_DEFINE 0x0
#define PHY_WRLVL_INIT_CS1_DEFINE 0x0
#define PHY_CTRL_SLAVE_RATIO_CS1_DEFINE 0x80
//- DDR2 parameters
#define DDR2_EMIF_DDRPHYCR_DEFINE 0x00173208
#define DDR2_EMIF_TIM1_DEFINE 0x0888E4E2
#define DDR2_EMIF_TIM2_DEFINE 0x202D31D2
#define DDR2_EMIF_TIM3_DEFINE 0x500002AF
#define DDR2_EMIF_REF_CTRL_DEFINE 0x00000A25
#define DDR2_EMIF_SDRAM_CONFIG_DEFINE 0x41801832
#define DDR2_PHY_0_RD_DQS_CS0_DEFINE 0x34
#define DDR2_PHY_0_WR_DQS_CS0_DEFINE 0x22
#define DDR2_PHY_0_RD_DQS_GATE_CS0_DEFINE 0xe4
#define DDR2_PHY_0_WR_DATA_CS0_DEFINE 0x48
#define DDR2_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE 0x80
#define DDR2_PHY_1_RD_DQS_CS0_DEFINE 0x32
#define DDR2_PHY_1_WR_DQS_CS0_DEFINE 0x22
#define DDR2_PHY_1_RD_DQS_GATE_CS0_DEFINE 0xf2
#define DDR2_PHY_1_WR_DATA_CS0_DEFINE 0x44
//- DDR3 parameters
#define DDR3_EMIF_REF_CTRL_DEFINE1 0x00004000
#define DDR3_EMIF_SDRAM_ZQCR_DEFINE 0x50074BE1
//DDR3 300 MHz - CL=5,CWL=5
#define DDR3_EMIF_TIM1_DEFINE_300 0x0888A394
#define DDR3_EMIF_TIM2_DEFINE_300 0x20237FE2
#define DDR3_EMIF_TIM3_DEFINE_300 0x501F820F
#define DDR3_EMIF_REF_CTRL_DEFINE2_300 0x00000924
#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_300 0x61C009B2
#define DDR3_EMIF_DDRPHYCR_DEFINE_300 0x00173208
//DDR3 333 MHz - CL=6,CWL=5
#define DDR3_EMIF_TIM1_DEFINE_333 0x0888B414
#define DDR3_EMIF_TIM2_DEFINE_333 0x20277FE2
#define DDR3_EMIF_TIM3_DEFINE_333 0x501F824F
#define DDR3_EMIF_REF_CTRL_DEFINE2_333 0x00000A25
#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_333 0x61C011B2
#define DDR3_EMIF_DDRPHYCR_DEFINE_333 0x00173209
//MODIFIED
//DDR3 400 MHz - CL=6,CWL=5
//TIM
#define DDR3_EMIF_TIM1_DEFINE_400 0x0AAAD4DB
#define DDR3_EMIF_TIM2_DEFINE_400 0x20437FDA
#define DDR3_EMIF_TIM3_DEFINE_400 0x531F83FF
//SDRRCR
#define DDR3_EMIF_REF_CTRL_DEFINE2_400 0x10000C30
//SDRCR
#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_400 0x61C012B3
//PHYCR
#define DDR3_EMIF_DDRPHYCR_DEFINE_400 0x0017320A
//DDR3 450 MHz - CL=7,CWL=6
#define DDR3_EMIF_TIM1_DEFINE_450 0x0CCCF55C
#define DDR3_EMIF_TIM2_DEFINE_450 0x30357FE2
#define DDR3_EMIF_TIM3_DEFINE_450 0x501F831F
#define DDR3_EMIF_REF_CTRL_DEFINE2_450 0x00000DB6
#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_450 0x61C119B2
#define DDR3_EMIF_DDRPHYCR_DEFINE_450 0x0017320A
//DDR3 533 MHz - CL=8,CWL=6
#define DDR3_EMIF_TIM1_DEFINE_533 0x0EEF2664
#define DDR3_EMIF_TIM2_DEFINE_533 0x303F7FE2
#define DDR3_EMIF_TIM3_DEFINE_533 0x501F83AF
#define DDR3_EMIF_REF_CTRL_DEFINE2_533 0x0000103D
#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_533 0x61C121B2
#define DDR3_EMIF_DDRPHYCR_DEFINE_533 0x0017320B
//DDR3 666 MHz - CL=9,CWL=7
#define DDR3_EMIF_TIM1_DEFINE_666 0x1333782C
#define DDR3_EMIF_TIM2_DEFINE_666 0x404F7FE2
#define DDR3_EMIF_TIM3_DEFINE_666 0x501F849F
#define DDR3_EMIF_REF_CTRL_DEFINE2_666 0x0000144A
#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_666 0x61C229B2
#define DDR3_EMIF_DDRPHYCR_DEFINE_666 0x0017320C
//MODIFIED DDR3 Timing Paramters
#define DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE 0x80
#define DDR3_PHY_0_RD_DQS_CS0_DEFINE 0x3d
#define DDR3_PHY_0_WR_DQS_CS0_DEFINE 0x1d
#define DDR3_PHY_0_RD_DQS_GATE_CS0_DEFINE 0x9b
#define DDR3_PHY_0_WR_DATA_CS0_DEFINE 0x3b
#define DDR3_PHY_1_RD_DQS_CS0_DEFINE 0x3d
#define DDR3_PHY_1_WR_DQS_CS0_DEFINE 0x1d
#define DDR3_PHY_1_RD_DQS_GATE_CS0_DEFINE 0x9b
#define DDR3_PHY_1_WR_DATA_CS0_DEFINE 0x3b
//- mDDR parameters
#define mDDR_EMIF_READ_LATENCY_DEFINE 0x5
#define mDDR_EMIF_TIM1_DEFINE 0x0888831B
#define mDDR_EMIF_TIM2_DEFINE 0x221A31C0
#define mDDR_EMIF_TIM3_DEFINE 0x00000157
#define mDDR_EMIF_REF_CTRL_DEFINE 0x10000618
#define mDDR_EMIF_SDRAM_CONFIG_DEFINE 0x20000EA2
#define mDDR_PHY_RD_DQS_CS0_DEFINE 0x42
#define mDDR_PHY_WR_DQS_CS0_DEFINE 0x19
#define mDDR_PHY_RD_DQS_GATE_CS0_DEFINE 0x128
#define mDDR_PHY_WR_DATA_CS0_DEFINE 0x56
#define mDDR_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE 0x80
//Pincntrl Configurations
#define PINCNTL68 (CTRL_MODULE_BASE_ADDR + 0x090C)
#define PINCNTL69 (CTRL_MODULE_BASE_ADDR + 0x0910)
#define PINCNTL72 (CTRL_MODULE_BASE_ADDR + 0x091C)
#define PINCNTL73 (CTRL_MODULE_BASE_ADDR + 0x0920)
#define PINCNTL59 (CTRL_MODULE_BASE_ADDR + 0x08e8)
#define PINCNTL60 (CTRL_MODULE_BASE_ADDR + 0x08ec)
#define PINCNTL89 (CTRL_MODULE_BASE_ADDR + 0x0960)
#define PINCNTL90 (CTRL_MODULE_BASE_ADDR + 0x0964)
#define PINCNTL91 (CTRL_MODULE_BASE_ADDR + 0x0968)
#define PINCNTL92 (CTRL_MODULE_BASE_ADDR + 0x096C)
#define PINCNTL93 (CTRL_MODULE_BASE_ADDR + 0x0970)
#define PINCNTL94 (CTRL_MODULE_BASE_ADDR + 0x0974)
#define PINCNTL95 (CTRL_MODULE_BASE_ADDR + 0x0978)
#define PINCNTL96 (CTRL_MODULE_BASE_ADDR + 0x097C)
#define PINCNTL97 (CTRL_MODULE_BASE_ADDR + 0x0980)
#define PINCNTL98 (CTRL_MODULE_BASE_ADDR + 0x0984)
#define PINCNTL99 (CTRL_MODULE_BASE_ADDR + 0x0988)
#define PINCNTL100 (CTRL_MODULE_BASE_ADDR + 0x098C)
#define PINCNTL101 (CTRL_MODULE_BASE_ADDR + 0x0990)
#define PINCNTL102 (CTRL_MODULE_BASE_ADDR + 0x0994)
#define PINCNTL103 (CTRL_MODULE_BASE_ADDR + 0x0998)
#define PINCNTL104 (CTRL_MODULE_BASE_ADDR + 0x099C)
#define PINCNTL105 (CTRL_MODULE_BASE_ADDR + 0x09A0)
#define PINCNTL106 (CTRL_MODULE_BASE_ADDR + 0x09A4)
#define PINCNTL107 (CTRL_MODULE_BASE_ADDR + 0x09A8)
#define PINCNTL108 (CTRL_MODULE_BASE_ADDR + 0x09AC)
#define PINCNTL109 (CTRL_MODULE_BASE_ADDR + 0x09B0)
#define PINCNTL110 (CTRL_MODULE_BASE_ADDR + 0x09B4)
#define PINCNTL111 (CTRL_MODULE_BASE_ADDR + 0x09B8)
#define PINCNTL112 (CTRL_MODULE_BASE_ADDR + 0x09BC)
#define PINCNTL122 (CTRL_MODULE_BASE_ADDR + 0x09E4)
#define PINCNTL123 (CTRL_MODULE_BASE_ADDR + 0x09E8)
#define PINCNTL124 (CTRL_MODULE_BASE_ADDR + 0x09EC)
#define PINCNTL125 (CTRL_MODULE_BASE_ADDR + 0x09F0)
#define PINCNTL126 (CTRL_MODULE_BASE_ADDR + 0x09F4)
#define PINCNTL127 (CTRL_MODULE_BASE_ADDR + 0x09F8)
#define PINCNTL128 (CTRL_MODULE_BASE_ADDR + 0x09FC)
#define PINCNTL129 (CTRL_MODULE_BASE_ADDR + 0x0A00)
#define PINCNTL130 (CTRL_MODULE_BASE_ADDR + 0x0A04)
#define PINCNTL131 (CTRL_MODULE_BASE_ADDR + 0x0A08)
#define PINCNTL132 (CTRL_MODULE_BASE_ADDR + 0x0A0C)
#define PINCNTL133 (CTRL_MODULE_BASE_ADDR + 0x0A10)
#define PINCNTL235 (CTRL_MODULE_BASE_ADDR + 0x0BA8)
#define PINCNTL243 (CTRL_MODULE_BASE_ADDR + 0x0BC8)
#define PINCNTL244 (CTRL_MODULE_BASE_ADDR + 0x0BCC)
#define PINCNTL245 (CTRL_MODULE_BASE_ADDR + 0x0BD0)
#define PINCNTL246 (CTRL_MODULE_BASE_ADDR + 0x0BD4)
#define PINCNTL247 (CTRL_MODULE_BASE_ADDR + 0x0BD8)
#define PINCNTL248 (CTRL_MODULE_BASE_ADDR + 0x0BDC)
#define PINCNTL249 (CTRL_MODULE_BASE_ADDR + 0x0BE0)
#define PINCNTL250 (CTRL_MODULE_BASE_ADDR + 0x0BE4)
#define PINCNTL251 (CTRL_MODULE_BASE_ADDR + 0x0BE8)
#define PINCNTL252 (CTRL_MODULE_BASE_ADDR + 0x0BEC)
#define PINCNTL253 (CTRL_MODULE_BASE_ADDR + 0x0BF0)
#define PINCNTL254 (CTRL_MODULE_BASE_ADDR + 0x0BF4)
#define PINCNTL255 (CTRL_MODULE_BASE_ADDR + 0x0BF8)
#define PINCNTL256 (CTRL_MODULE_BASE_ADDR + 0x0BFC)
#define PINCNTL257 (CTRL_MODULE_BASE_ADDR + 0x0C00)
#define PINCNTL258 (CTRL_MODULE_BASE_ADDR + 0x0C04)
#define WR_MEM_32(addr, data) *(unsigned int*)(addr)=(unsigned int)(data)
#define RD_MEM_32(addr) *(unsigned int*)(addr)
#define UWORD32 unsigned int
/*** PLL,Control Base Adress Base Address ***********/
#define PLL_BASE_ADDRESS 0x481C5000
#define CONTROL_BASE_ADDRESS 0x48140000
#define OSC_SRC_CTRL (PLL_BASE_ADDRESS+0x02c0)
#define ARM_SRC_CLK (PLL_BASE_ADDRESS+0x02c4)
/*** Top Level ADPLLJ Base Address ***********/
#define L3_PLL_BASE (PLL_BASE_ADDRESS+0x110)
#define IVA_PLL_BASE (PLL_BASE_ADDRESS+0x0E0)
#define DSS_PLL_BASE (PLL_BASE_ADDRESS+0x170)
#define SGX_PLL_BASE (PLL_BASE_ADDRESS+0x0B0)
#define DSP_PLL_BASE (PLL_BASE_ADDRESS+0x080)
#define ISS_PLL_BASE (PLL_BASE_ADDRESS+0x140)
#define USB_PLL_BASE (PLL_BASE_ADDRESS+0x260)
#define AUDIO_PLL_BASE (PLL_BASE_ADDRESS+0x230)
#define VIDEO_0_PLL_BASE (PLL_BASE_ADDRESS+0x1A0)
#define VIDEO_1_PLL_BASE (PLL_BASE_ADDRESS+0x1D0)
#define HDMI_PLL_BASE (PLL_BASE_ADDRESS+0x200)
#define DDR_PLL_BASE (PLL_BASE_ADDRESS+0x290)
/********** ADPLL intrnal Offset Registers ***********/
#define CLKCTRL 0x4
#define TENABLE 0x8
#define TENABLEDIV 0xC
#define M2NDIV 0x10
#define MN2DIV 0x14
#define STATUS 0x24
/*********** MODENA ADPLLS REGISTERS *********/
#define MODENAPLL_CLKCTRL (PLL_BASE_ADDRESS+0x04c)
#define MODENAPLL_TENABLE (PLL_BASE_ADDRESS+0x050)
#define MODENAPLL_TENABLEDIV (PLL_BASE_ADDRESS+0x054)
#define MODENAPLL_M2NDIV (PLL_BASE_ADDRESS+0x058)
#define MODENAPLL_MN2DIV (PLL_BASE_ADDRESS+0x05c)
#define MODENAPLL_STATUS (PLL_BASE_ADDRESS+0x06c)
/******** SATA PLL REGISTERS **************/
#define SATA_PLLCFG0 (CONTROL_BASE_ADDRESS+0x720)
#define SATA_PLLCFG1 (CONTROL_BASE_ADDRESS+0x724)
#define SATA_PLLCFG2 (CONTROL_BASE_ADDRESS+0x728)
#define SATA_PLLCFG3 (CONTROL_BASE_ADDRESS+0x72c)
#define SATA_PLLCFG4 (CONTROL_BASE_ADDRESS+0x730)
#define SATA_PLLSTATUS (CONTROL_BASE_ADDRESS+0x734)
#define SATA_RXSTATUS (CONTROL_BASE_ADDRESS+0x738)
#define SATA_TXSTATUS (CONTROL_BASE_ADDRESS+0x73c)
/******** PCIE PLL REGISTERS **************/
#define PCIE_PLLCFG0 (CONTROL_BASE_ADDRESS+0x6D8)
#define PCIE_PLLCFG1 (CONTROL_BASE_ADDRESS+0x6DC)
#define PCIE_PLLCFG2 (CONTROL_BASE_ADDRESS+0x6E0)
#define PCIE_PLLCFG3 (CONTROL_BASE_ADDRESS+0x6E4)
#define PCIE_PLLCFG4 (CONTROL_BASE_ADDRESS+0x6E8)
#define PCIE_PLLSTATUS (CONTROL_BASE_ADDRESS+0x6EC)
#define PCIE_RXSTATUS (CONTROL_BASE_ADDRESS+0x6F0)
#define PCIE_TXSTATUS (CONTROL_BASE_ADDRESS+0x6F4)
#define SERDES_REFCLK_CTL (CONTROL_BASE_ADDRESS+0xE24)
#define CONTROL_STATUS (CTRL_MODULE_BASE_ADDR + 0x040)
#define BANDGAP0_TRIM (CTRL_MODULE_BASE_ADDR + 0x44C)
#define BANDGAP1_TRIM (CTRL_MODULE_BASE_ADDR + 0x454)
#define PLL_SUBSYSTEM_BASE_ADDR PLL_BASE_ADDRESS
#define DSPPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x084)
#define SGXPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x0B4)
#define IVAPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x0E4)
#define L3PLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x114)
#define ISSPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x144)
#define DSSPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x174)
#define VID0PLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x1A4)
#define VID1PLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x1D4)
#define HDMIPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x204)
#define AUDIOPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x234)
#define USBPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x264)
#define DDRPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x294)
#define MODENAPLL_CLOCK_CONTROL (PLL_SUBSYSTEM_BASE_ADDR + 0x04C)
/*************************************************************************************************************
ADPLLJ CLKCNTRL REGISTER CONFIGURATIONS
***************************************************************************************************************/
// ADPLLJ_CLKCRTL_Register Value Configurations
#define ADPLLJ_CLKCRTL_HS2 0x00000801 //HS2 Mode,TINTZ =1 --used by all PLL's except HDMI
#define ADPLLJ_CLKCRTL_HS1 0x00001001 //HS1 Mode,TINTZ =1 --used only for HDMI
#define ADPLLJ_CLKCRTL_CLKDCO 0x200a0000 // Enable CLKDCOEN,CLKLDOEN,CLKDCOPWDNZ -- used for HDMI,USB
/****************************************************************************************************************/
// CONTROL MMMR LOCK and UNLOCK Registers
#define control_pllss_mmr_lock 0x481C5040
#define control_mmr_lock0 0x48140060
#define control_mmr_lock1 0x48140064
#define control_mmr_lock2 0x48140068
#define control_mmr_lock3 0x4814006c
#define control_mmr_lock4 0x48140070
#define control_pllss_mmr_lock_unlock_val 0x1EDA4C3D
#define control_mmr_lock0_unlock_val 0x2FF1AC2B
#define control_mmr_lock1_unlock_val 0xF757FDC0
#define control_mmr_lock2_unlock_val 0xE2BC3A6D
#define control_mmr_lock3_unlock_val 0x1EBF131D
#define control_mmr_lock4_unlock_val 0x6F361E05
/****************************************************************************************************************
****************************************************************************************************************/
/*******************************************************************************************************
****
**** ********* RANGE ************
**** REF_CLK = (OSC_FREQ)/N+1 [ REF_CLK < 2.5MHz ]
**** DCOCLK_HS2 = (REF_CLK)*M [500 < DCOCLK < 1000MHz ]
**** DCOCLK_HS1 = (REF_CLK)*M [1000 < DCOCLK < 2000MHz ]--used for HDMI CLKDCO
**** CLKOUT = DCOCLK/M2 [10 < CLKOUT < 2000MHz ]
**** N+1 [1..256]
**** M [2..4095]
**** M2 [1..127]
****
****
******************************************************************************************************/
/***************************************************************/
int HSMODE,CLKOUT = 0;
PLL_SETUP(){
//pll_name (CLKINP,N , M, M2);
cmdMPUPLL(CLKIN,1, 60 ,1);
cmdL3PLL(CLKIN,19,800,4);
cmdDSPPLL(CLKIN,19, 500, 1);
cmdDSSPLL(CLKIN,19, 800, 4);
cmdISSPLL(CLKIN,19, 800 ,2);
cmdIVAPLL(CLKIN,19, 532, 2);
cmdSGXPLL(CLKIN,19, 800, 4);
cmdUSBPLL(CLKIN,19,960,5);
cmdVIDEO0PLL(CLKIN,19, 540,10);
cmdVIDEO1PLL(CLKIN,19, 594,4);
cmdHDMIPLL(CLKIN,19, 1485,10);
// cmdDDRPLL(CLKIN,19,DDR_FREQ, 2); //DDR PLL config now done as a part of DDR hotmenus
cmdAUDIOPLL(CLKIN,19,800,4);
//cmdSATAPLL();
//cmdPCIEPLL();
}
cmdMPUPLL(int CLKIN,int N, int M, int M2)
{
MODENA_PLL_Config(CLKIN,N,M,M2);
GEL_TextOut("\t MODENA ADPLLJ CLKOUT value is = %d \n",,,,,CLKOUT);
}
cmdL3PLL(int CLKIN,int N, int M, int M2)
{
DCOCLK_COMP(CLKIN,N,M);
if(HSMODE == 2){
PLL_Clocks_Config(L3_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2);
GEL_TextOut("\t L3 ADPLLJ CLKOUT value is = %d \n",,,,,CLKOUT);
}
else if (HSMODE == 1){
PLL_Clocks_Config(L3_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1);
GEL_TextOut("\t L3 ADPLLJ CLKOUT value is = %d \n",,,,,CLKOUT);
}
else {
GEL_TextOut("\t L3 PLL NOT Configured.Wrong DCOCLK Output\n");
}
}
cmdDDRPLL(int CLKIN,int N, int M, int M2)
{
DCOCLK_COMP(CLKIN,N,M);
if(HSMODE == 2){
PLL_Clocks_Config(DDR_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2);
GEL_TextOut("\tDM814x DDR DPLL CLKOUT value is = %d \n",,,,,CLKOUT);
}
else if (HSMODE == 1){
PLL_Clocks_Config(DDR_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1);
GEL_TextOut("\tDM814x DDR DPLL CLKOUT value is = %d \n",,,,,CLKOUT);
}
else {
GEL_TextOut("\t DDR PLL NOT Configured.Wrong DCOCLK Output\n");
}
}
int CLKIN = 20;
wait_delay(UWORD32 noopcount)
{
int i;
for(i=0;i<noopcount;i++)
{
}
}
PLL_Clocks_Config(UWORD32 Base_Address,UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2,UWORD32 CLKCTRL_VAL)
{
UWORD32 m2nval,mn2val,read_clkctrl,clk_out,ref_clk,clkout_dco = 0;
m2nval = (M2<<16) | N;
mn2val = M;
ref_clk = CLKIN/(N+1);
clkout_dco = ref_clk*M;
clk_out = clkout_dco/M2;
WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)|0x00800000);
while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000101) != 0x00000101);
WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)& 0xfffffffe);
wait_delay(3);
WR_MEM_32((Base_Address+M2NDIV ),m2nval);
WR_MEM_32((Base_Address+MN2DIV ),mn2val);
wait_delay(3);
WR_MEM_32((Base_Address+TENABLEDIV),0x1);
wait_delay(3);
WR_MEM_32((Base_Address+TENABLEDIV),0x0);
wait_delay(3);
WR_MEM_32((Base_Address+TENABLE ),0x1);
wait_delay(3);
WR_MEM_32((Base_Address+TENABLE ),0x0);
wait_delay(3);
read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
//configure the TINITZ(bit0) and CLKDCO BITS IF REQUIRED
WR_MEM_32(Base_Address+CLKCTRL,(read_clkctrl & 0xff7fe3ff) | CLKCTRL_VAL);
read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
// poll for the freq,phase lock to occur
while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000600) != 0x00000600);
//wait fot the clocks to get stabized
wait_delay(10);
CLKOUT = clk_out;
}
MODENA_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
{
UWORD32 rval_ctrl,ref_clk,clk_out = 0;
UWORD32 m2nval,mn2val = 0;
ref_clk = CLKIN/(N+1);
clk_out = (ref_clk*M)/M2;
m2nval = (M2<<16) | N; //need to check the bit position of M2
mn2val = M;
WR_MEM_32(MODENAPLL_M2NDIV ,m2nval);
WR_MEM_32(MODENAPLL_MN2DIV ,mn2val);
WR_MEM_32(MODENAPLL_TENABLEDIV ,0x1);
wait_delay(3);
WR_MEM_32(MODENAPLL_TENABLEDIV ,0x0);
wait_delay(3);
WR_MEM_32(MODENAPLL_TENABLE ,0x1);
wait_delay(3);
WR_MEM_32(MODENAPLL_TENABLE ,0x0);
wait_delay(3);
rval_ctrl = RD_MEM_32(MODENAPLL_CLKCTRL);
WR_MEM_32(MODENAPLL_CLKCTRL,(rval_ctrl & 0xff7fffff) | 0x1);
while (( (RD_MEM_32(MODENAPLL_STATUS)) & 0x00000600) != 0x00000600);
wait_delay(10);
CLKOUT = clk_out;
}
DCOCLK_COMP(int CLKIN,int N, int M)
{
int DCOCLK;
DCOCLK = (CLKIN/(N+1))*M;
if(DCOCLK >= 500 && DCOCLK < 1000){
HSMODE = 2; //HS2 Mode
}
else if(DCOCLK >= 1000 && DCOCLK < 2000){
HSMODE = 1; //HS1 Mode
}
else HSMODE = 0; //wrong configuration
}
ControlModule_ClkEnable()
{
GEL_TextOut("\tPRCM for Control Module in Progress \n");
//Enable the Clocks
WR_MEM_32(CM_CTRL_CLKCTRL, 2);
while(((RD_MEM_32(CM_CTRL_CLKCTRL)&0x30000))!=0x30000);
GEL_TextOut("\tPRCM for Control Module Done \n");
}
PrcmAlwayOnClkEnable()
{
unsigned int fail=0, k=0;
GEL_TextOut("\tPRCM for OCMCRAM0/1 Initialization in Progress \n");
/*Enable the OCMC0RAM Clocks*/
WR_MEM_32(CM_ALWON_OCMC_0_CLKSTCTRL, 2);
WR_MEM_32(CM_ALWON_OCMC_0_CLKCTRL, 2);
while(((RD_MEM_32(CM_ALWON_OCMC_0_CLKSTCTRL) & 0x100)>>8)!=1);
while(((RD_MEM_32(CM_ALWON_OCMC_0_CLKCTRL)&0x30000)>>17)!=0);
GEL_TextOut("\tPRCM for OCMCRAM0 Initialization Done \n");
/*for(k=0; k<SIZE; k++) {
WR_MEM_32(OCMC0RAM_BASE_ADDR+4*k, 0x12345678+k);
}
for(k=0; k<SIZE; k++) {
if(RD_MEM_32(OCMC0RAM_BASE_ADDR+4*k) != (0x12345678+k) ) {
fail++;
}
}
if(fail!=0) {
GEL_TextOut("\tOCMCRAM0 Accesses FAILED \n");
}
GEL_TextOut("\tOCMCRAM0 Accesses PASSED \n");
*/
}
Unlock_PLL_Control_MMR()
{
WR_MEM_32(control_pllss_mmr_lock,control_pllss_mmr_lock_unlock_val);
WR_MEM_32(control_mmr_lock0,control_mmr_lock0_unlock_val);
WR_MEM_32(control_mmr_lock1,control_mmr_lock1_unlock_val);
WR_MEM_32(control_mmr_lock2,control_mmr_lock2_unlock_val);
WR_MEM_32(control_mmr_lock3,control_mmr_lock3_unlock_val);
WR_MEM_32(control_mmr_lock4,control_mmr_lock4_unlock_val);
GEL_TextOut("\n PLL and Control MMR unlock done ... \n");
}
hotmenu ADPLL_CLOCKS_ENABLE_API()
{
GEL_TextOut("\t **** TIDM814x ADPLL INIT is in progress ......... \n");
PLL_SETUP();
GEL_TextOut("\t **** TIDM814x ADPLL INIT is completed *********** \n");
}
ControlModule_ClkEnable_API()
{
ControlModule_ClkEnable();
}
PrcmAlwayOnClkEnable_API()
{
PrcmAlwayOnClkEnable();
}
/*******************************************************************************************************
EMIF/DDR FUNCTIONS
********************************************************************************************************************/
cmd_DDR2_EMIF0_EMIF1_Config(UWORD32 ddr2_phy_0_rd_dqs_cs0_arg,UWORD32 ddr2_phy_0_wr_dqs_cs0_arg,UWORD32 ddr2_phy_0_RD_DQS_GATE_cs0_arg,UWORD32 ddr2_phy_0_wr_data_cs0_arg,UWORD32 ddr2_phy_1_rd_dqs_cs0_arg,UWORD32 ddr2_phy_1_wr_dqs_cs0_arg,UWORD32 ddr2_phy_1_RD_DQS_GATE_cs0_arg,UWORD32 ddr2_phy_1_wr_data_cs0_arg,UWORD32 ddr2_emif_read_latency_arg,UWORD32 ddr2_emif_tim1_arg,UWORD32 ddr2_emif_tim2_arg,UWORD32 ddr2_emif_tim3_arg,UWORD32 ddr2_emif_ref_ctrl_arg,UWORD32 ddr2_emif_sdram_config_arg)
{
Emif_PRCM_Clk_Enable();
GEL_TextOut("\tDM814x DDR,DMM PRCM configuration is Done \n");
Cmd_Macro_Config(DDR_PHY0,PHY_INVERT_CLKOUT_DEFINE,DDR2_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE,PHY_CMD0_DLL_LOCK_DIFF_DEFINE);
Data_Macro_Config(DATA_MACRO_0,DDR_PHY0,ddr2_phy_0_rd_dqs_cs0_arg,ddr2_phy_0_wr_dqs_cs0_arg,ddr2_phy_0_RD_DQS_GATE_cs0_arg,ddr2_phy_0_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_1,DDR_PHY0,ddr2_phy_0_rd_dqs_cs0_arg,ddr2_phy_0_wr_dqs_cs0_arg,ddr2_phy_0_RD_DQS_GATE_cs0_arg,ddr2_phy_0_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_2,DDR_PHY0,ddr2_phy_0_rd_dqs_cs0_arg,ddr2_phy_0_wr_dqs_cs0_arg,ddr2_phy_0_RD_DQS_GATE_cs0_arg,ddr2_phy_0_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_3,DDR_PHY0,ddr2_phy_0_rd_dqs_cs0_arg,ddr2_phy_0_wr_dqs_cs0_arg,ddr2_phy_0_RD_DQS_GATE_cs0_arg,ddr2_phy_0_wr_data_cs0_arg);
Cmd_Macro_Config(DDR_PHY1,PHY_INVERT_CLKOUT_DEFINE,DDR2_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE,PHY_CMD0_DLL_LOCK_DIFF_DEFINE);
Data_Macro_Config(DATA_MACRO_0,DDR_PHY1,ddr2_phy_1_rd_dqs_cs0_arg,ddr2_phy_1_wr_dqs_cs0_arg,ddr2_phy_1_RD_DQS_GATE_cs0_arg,ddr2_phy_1_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_1,DDR_PHY1,ddr2_phy_1_rd_dqs_cs0_arg,ddr2_phy_1_wr_dqs_cs0_arg,ddr2_phy_1_RD_DQS_GATE_cs0_arg,ddr2_phy_1_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_2,DDR_PHY1,ddr2_phy_1_rd_dqs_cs0_arg,ddr2_phy_1_wr_dqs_cs0_arg,ddr2_phy_1_RD_DQS_GATE_cs0_arg,ddr2_phy_1_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_3,DDR_PHY1,ddr2_phy_1_rd_dqs_cs0_arg,ddr2_phy_1_wr_dqs_cs0_arg,ddr2_phy_1_RD_DQS_GATE_cs0_arg,ddr2_phy_1_wr_data_cs0_arg);
GEL_TextOut("\tDM814x DDR PHY Configuration is Done \n");
WR_MEM_32(DDR0_IO_CTRL,0x00030303);
WR_MEM_32(DDR1_IO_CTRL,0x00030303);
GEL_TextOut("\tDM814x DDR IO Control Configuration is Done \n");
Vtp_Enable();
GEL_TextOut("\tDM814x VTP Configuration is Done \n");
/*Program the DMM to Access EMIF0 and EMIF1*/
WR_MEM_32(DMM_LISA_MAP__0, 0x80600100);
WR_MEM_32(DMM_LISA_MAP__1, 0x80600100);
WR_MEM_32(DMM_LISA_MAP__2, 0xC0600200);
WR_MEM_32(DMM_LISA_MAP__3, 0xC0600200);
while(RD_MEM_32(DMM_LISA_MAP__0)!=0x80600100);
while(RD_MEM_32(DMM_LISA_MAP__1)!=0x80600100);
while(RD_MEM_32(DMM_LISA_MAP__2)!=0xC0600200);
while(RD_MEM_32(DMM_LISA_MAP__3)!=0xC0600200);
WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);
GEL_TextOut("\tDM814x DMM LISA register Configuration is Done\n");
Emif0_MMR_Config(ddr2_emif_read_latency_arg,ddr2_emif_tim1_arg,ddr2_emif_tim2_arg,ddr2_emif_tim3_arg,ddr2_emif_ref_ctrl_arg,ddr2_emif_sdram_config_arg);
Emif1_MMR_Config(ddr2_emif_read_latency_arg,ddr2_emif_tim1_arg,ddr2_emif_tim2_arg,ddr2_emif_tim3_arg,ddr2_emif_ref_ctrl_arg,ddr2_emif_sdram_config_arg);
}
cmd_DDR3_EMIF0_EMIF1_Config(UWORD32 ddr3_phy_0_rd_dqs_cs0_arg,UWORD32 ddr3_phy_0_wr_dqs_cs0_arg,UWORD32 ddr3_phy_0_RD_DQS_GATE_cs0_arg,UWORD32 ddr3_phy_0_wr_data_cs0_arg,UWORD32 ddr3_phy_1_rd_dqs_cs0_arg,UWORD32 ddr3_phy_1_wr_dqs_cs0_arg,UWORD32 ddr3_phy_1_RD_DQS_GATE_cs0_arg,UWORD32 ddr3_phy_1_wr_data_cs0_arg,UWORD32 ddr3_emif_read_latency_arg,UWORD32 ddr3_emif_tim1_arg,UWORD32 ddr3_emif_tim2_arg,UWORD32 ddr3_emif_tim3_arg,UWORD32 ddr3_emif_ref_ctrl_arg,UWORD32 ddr3_emif_sdram_config_arg)
{
Emif_PRCM_Clk_Enable();
GEL_TextOut("\tDM814x DDR,DMM PRCM configuration is Done \n");
Cmd_Macro_Config(DDR_PHY0,DDR3_PHY_INVERT_CLKOUT_OFF,DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE,PHY_CMD0_DLL_LOCK_DIFF_DEFINE);
Data_Macro_Config(DATA_MACRO_0,DDR_PHY0,ddr3_phy_0_rd_dqs_cs0_arg,ddr3_phy_0_wr_dqs_cs0_arg,ddr3_phy_0_RD_DQS_GATE_cs0_arg,ddr3_phy_0_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_1,DDR_PHY0,ddr3_phy_0_rd_dqs_cs0_arg,ddr3_phy_0_wr_dqs_cs0_arg,ddr3_phy_0_RD_DQS_GATE_cs0_arg,ddr3_phy_0_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_2,DDR_PHY0,ddr3_phy_0_rd_dqs_cs0_arg,ddr3_phy_0_wr_dqs_cs0_arg,ddr3_phy_0_RD_DQS_GATE_cs0_arg,ddr3_phy_0_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_3,DDR_PHY0,ddr3_phy_0_rd_dqs_cs0_arg,ddr3_phy_0_wr_dqs_cs0_arg,ddr3_phy_0_RD_DQS_GATE_cs0_arg,ddr3_phy_0_wr_data_cs0_arg);
Cmd_Macro_Config(DDR_PHY1,DDR3_PHY_INVERT_CLKOUT_OFF,DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE,PHY_CMD0_DLL_LOCK_DIFF_DEFINE);
Data_Macro_Config(DATA_MACRO_0,DDR_PHY1,ddr3_phy_1_rd_dqs_cs0_arg,ddr3_phy_1_wr_dqs_cs0_arg,ddr3_phy_1_RD_DQS_GATE_cs0_arg,ddr3_phy_1_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_1,DDR_PHY1,ddr3_phy_1_rd_dqs_cs0_arg,ddr3_phy_1_wr_dqs_cs0_arg,ddr3_phy_1_RD_DQS_GATE_cs0_arg,ddr3_phy_1_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_2,DDR_PHY1,ddr3_phy_1_rd_dqs_cs0_arg,ddr3_phy_1_wr_dqs_cs0_arg,ddr3_phy_1_RD_DQS_GATE_cs0_arg,ddr3_phy_1_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_3,DDR_PHY1,ddr3_phy_1_rd_dqs_cs0_arg,ddr3_phy_1_wr_dqs_cs0_arg,ddr3_phy_1_RD_DQS_GATE_cs0_arg,ddr3_phy_1_wr_data_cs0_arg);
GEL_TextOut("\tDM814x DDR PHY Configuration is Done \n");
WR_MEM_32(DDR0_IO_CTRL,0x00030303);
WR_MEM_32(DDR1_IO_CTRL,0x00030303);
GEL_TextOut("\tDM814x DDR IO Control Configuration is Done \n");
Vtp_Enable();
GEL_TextOut("\tDM814x VTP Configuration is Done \n");
/*Program the DMM to Access EMIF0 and EMIF1*/
WR_MEM_32(DMM_LISA_MAP__0, 0x80500200);
WR_MEM_32(DMM_LISA_MAP__1, 0xA0500200);
WR_MEM_32(DMM_LISA_MAP__2, 0xC0500100);
WR_MEM_32(DMM_LISA_MAP__3, 0xE0500100);
while(RD_MEM_32(DMM_LISA_MAP__0)!=0x80500200);
while(RD_MEM_32(DMM_LISA_MAP__1)!=0xA0500200);
while(RD_MEM_32(DMM_LISA_MAP__2)!=0xC0500100);
while(RD_MEM_32(DMM_LISA_MAP__3)!=0xE0500100);
WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);
GEL_TextOut("\tDM814x DMM LISA register Configuration is Done.\n");
Emif0_MMR_Config(ddr3_emif_read_latency_arg,ddr3_emif_tim1_arg,ddr3_emif_tim2_arg,ddr3_emif_tim3_arg,ddr3_emif_ref_ctrl_arg,ddr3_emif_sdram_config_arg);
Emif1_MMR_Config(ddr3_emif_read_latency_arg,ddr3_emif_tim1_arg,ddr3_emif_tim2_arg,ddr3_emif_tim3_arg,ddr3_emif_ref_ctrl_arg,ddr3_emif_sdram_config_arg);
/*TODO: put comments if full leveling is not needed*/
//GEL_TextOut("\tDM814x DMM Leveling Start.\n");
//WR_MEM_32(EMIF4_1_RDWR_LVL_RMP_CTRL, 0x80000000); //- Bit 31 = 1;
//WR_MEM_32(EMIF4_1_RDWR_LVL_CTRL, 0x80000000); //- Bit 31 = 1;
//GEL_TextOut("\tDM814x DMM Leveling Done.\n");
}
cmd_mDDR_EMIF0_EMIF1_Config(UWORD32 mDDR_phy_rd_dqs_cs0_arg,UWORD32 mDDR_phy_wr_dqs_cs0_arg,UWORD32 mDDR_phy_RD_DQS_GATE_cs0_arg,UWORD32 mDDR_phy_wr_data_cs0_arg,UWORD32 mDDR_emif_read_latency_arg,UWORD32 mDDR_emif_tim1_arg,UWORD32 mDDR_emif_tim2_arg,UWORD32 mDDR_emif_tim3_arg,UWORD32 mDDR_emif_ref_ctrl_arg,UWORD32 mDDR_emif_sdram_config_arg)
{
UWORD32 i;
Emif_PRCM_Clk_Enable();
Cmd_Macro_Config(DDR_PHY0,PHY_INVERT_CLKOUT_DEFINE,mDDR_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE,PHY_CMD0_DLL_LOCK_DIFF_DEFINE);
Data_Macro_Config(DATA_MACRO_0,ddr_phy0,mDDR_phy_rd_dqs_cs0_arg,mDDR_phy_wr_dqs_cs0_arg,mDDR_phy_RD_DQS_GATE_cs0_arg,mDDR_phy_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_1,ddr_phy0,mDDR_phy_rd_dqs_cs0_arg,mDDR_phy_wr_dqs_cs0_arg,mDDR_phy_RD_DQS_GATE_cs0_arg,mDDR_phy_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_2,ddr_phy0,mDDR_phy_rd_dqs_cs0_arg,mDDR_phy_wr_dqs_cs0_arg,mDDR_phy_RD_DQS_GATE_cs0_arg,mDDR_phy_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_3,ddr_phy0,mDDR_phy_rd_dqs_cs0_arg,mDDR_phy_wr_dqs_cs0_arg,mDDR_phy_RD_DQS_GATE_cs0_arg,mDDR_phy_wr_data_cs0_arg);
Cmd_Macro_Config(DDR_PHY1,PHY_INVERT_CLKOUT_DEFINE,mDDR_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE,PHY_CMD0_DLL_LOCK_DIFF_DEFINE);
Data_Macro_Config(DATA_MACRO_0,ddr_phy1,mDDR_phy_rd_dqs_cs0_arg,mDDR_phy_wr_dqs_cs0_arg,mDDR_phy_RD_DQS_GATE_cs0_arg,mDDR_phy_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_1,ddr_phy1,mDDR_phy_rd_dqs_cs0_arg,mDDR_phy_wr_dqs_cs0_arg,mDDR_phy_RD_DQS_GATE_cs0_arg,mDDR_phy_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_2,ddr_phy1,mDDR_phy_rd_dqs_cs0_arg,mDDR_phy_wr_dqs_cs0_arg,mDDR_phy_RD_DQS_GATE_cs0_arg,mDDR_phy_wr_data_cs0_arg);
Data_Macro_Config(DATA_MACRO_3,ddr_phy1,mDDR_phy_rd_dqs_cs0_arg,mDDR_phy_wr_dqs_cs0_arg,mDDR_phy_RD_DQS_GATE_cs0_arg,mDDR_phy_wr_data_cs0_arg);
WR_MEM_32(DATA0_REG_PHY0_USE_RANK0_DELAYS, mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE);
WR_MEM_32(DATA1_REG_PHY0_USE_RANK0_DELAYS, mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE);
WR_MEM_32(DATA2_REG_PHY0_USE_RANK0_DELAYS, mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE);
WR_MEM_32(DATA3_REG_PHY0_USE_RANK0_DELAYS, mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE);
WR_MEM_32(DATA0_REG_PHY1_USE_RANK0_DELAYS, mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE);
WR_MEM_32(DATA1_REG_PHY1_USE_RANK0_DELAYS, mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE);
WR_MEM_32(DATA2_REG_PHY1_USE_RANK0_DELAYS, mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE);
WR_MEM_32(DATA3_REG_PHY1_USE_RANK0_DELAYS, mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE);
WR_MEM_32(DDR0_IO_CTRL,0x10030303);
WR_MEM_32(DDR1_IO_CTRL,0x10030303);
Vtp_Enable();
/*Program the DMM to Access EMIF0 and EMIF1*/
WR_MEM_32(DMM_LISA_MAP__0, 0x80500100);
WR_MEM_32(DMM_LISA_MAP__1, 0x80500100);
WR_MEM_32(DMM_LISA_MAP__2, 0xC0500200);
WR_MEM_32(DMM_LISA_MAP__3, 0xC0500200);
while(RD_MEM_32(DMM_LISA_MAP__0)!=0x80500100);
while(RD_MEM_32(DMM_LISA_MAP__1)!=0x80500100);
while(RD_MEM_32(DMM_LISA_MAP__2)!=0xC0500200);
while(RD_MEM_32(DMM_LISA_MAP__3)!=0xC0500200);
WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);
Emif0_MMR_Config(mDDR_emif_read_latency_arg,mDDR_emif_tim1_arg,mDDR_emif_tim2_arg,mDDR_emif_tim3_arg,mDDR_emif_ref_ctrl_arg,mDDR_emif_sdram_config_arg);
Emif1_MMR_Config(mDDR_emif_read_latency_arg,mDDR_emif_tim1_arg,mDDR_emif_tim2_arg,mDDR_emif_tim3_arg,mDDR_emif_ref_ctrl_arg,mDDR_emif_sdram_config_arg);
}
Data_Macro_Config(UWORD32 dataMacroNum,UWORD32 ddr_phy_num,UWORD32 rd_dqs_cs0,UWORD32 wr_dqs_cs0,UWORD32 RD_DQS_GATE_cs0,UWORD32 wr_data_cs0)
{
UWORD32 BaseAddrOffset;
if(dataMacroNum == DATA_MACRO_0)
BaseAddrOffset = 0x00;
else if(dataMacroNum == DATA_MACRO_1)
BaseAddrOffset = 0xA4;
else if(dataMacroNum == DATA_MACRO_2)
BaseAddrOffset = 0x148;
else if(dataMacroNum == DATA_MACRO_3)
BaseAddrOffset = 0x1EC;
if(ddr_phy_num == DDR_PHY1)
BaseAddrOffset = BaseAddrOffset + 0x400;//- phy1 is at offset of 0x400 from phy0
WR_MEM_32((DATA0_REG_PHY0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset), (rd_dqs_cs0 << 10 | rd_dqs_cs0));
WR_MEM_32((DATA0_REG_PHY0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset), (wr_dqs_cs0 << 10 | wr_dqs_cs0));
WR_MEM_32((DATA0_REG_PHY0_WRLVL_INIT_RATIO_0 + BaseAddrOffset), (PHY_WRLVL_INIT_CS1_DEFINE << 10 | PHY_WRLVL_INIT_CS0_DEFINE));
WR_MEM_32((DATA0_REG_PHY0_GATELVL_INIT_RATIO_0 + BaseAddrOffset), (PHY_GATELVL_INIT_CS1_DEFINE << 10 | PHY_GATELVL_INIT_CS0_DEFINE));
WR_MEM_32((DATA0_REG_PHY0_RD_DQS_GATE_SLAVE_RATIO_0 + BaseAddrOffset),(RD_DQS_GATE_cs0 << 10 | RD_DQS_GATE_cs0));
WR_MEM_32((DATA0_REG_PHY0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset),(wr_data_cs0 << 10 | wr_data_cs0));
//-WR_MEM_32((DATA0_REG_PHY0_USE_RANK0_DELAYS + BaseAddrOffset), PHY_REG_USE_RANK0_DELAY_DEFINE);//- default is 0; for mDDR need to set as 1
WR_MEM_32((DATA0_REG_PHY0_DLL_LOCK_DIFF_0 + BaseAddrOffset), PHY_DLL_LOCK_DIFF_DEFINE);
}
Cmd_Macro_Config(UWORD32 ddr_phy_num,UWORD32 invert_clk_out,UWORD32 ctrl_slave_ratio_cs0,UWORD32 cmd_dll_lock_diff)
{
if(ddr_phy_num == DDR_PHY0)
{
WR_MEM_32(CMD0_REG_PHY0_INVERT_CLKOUT_0, invert_clk_out);
WR_MEM_32(CMD1_REG_PHY0_INVERT_CLKOUT_0, invert_clk_out);
WR_MEM_32(CMD2_REG_PHY0_INVERT_CLKOUT_0, invert_clk_out);
WR_MEM_32(CMD0_REG_PHY0_CTRL_SLAVE_RATIO_0,(ctrl_slave_ratio_cs0 << 10 | ctrl_slave_ratio_cs0));
WR_MEM_32(CMD1_REG_PHY0_CTRL_SLAVE_RATIO_0,(ctrl_slave_ratio_cs0 << 10 | ctrl_slave_ratio_cs0));
WR_MEM_32(CMD2_REG_PHY0_CTRL_SLAVE_RATIO_0,(ctrl_slave_ratio_cs0 << 10 | ctrl_slave_ratio_cs0));
WR_MEM_32(CMD0_REG_PHY0_DLL_LOCK_DIFF_0,cmd_dll_lock_diff);
WR_MEM_32(CMD1_REG_PHY0_DLL_LOCK_DIFF_0,cmd_dll_lock_diff);
WR_MEM_32(CMD2_REG_PHY0_DLL_LOCK_DIFF_0,cmd_dll_lock_diff);
}
else if(ddr_phy_num == DDR_PHY1)
{
WR_MEM_32(CMD0_REG_PHY1_INVERT_CLKOUT_0, invert_clk_out);
WR_MEM_32(CMD1_REG_PHY1_INVERT_CLKOUT_0, invert_clk_out);
WR_MEM_32(CMD2_REG_PHY1_INVERT_CLKOUT_0, invert_clk_out);
WR_MEM_32(CMD0_REG_PHY1_CTRL_SLAVE_RATIO_0,(ctrl_slave_ratio_cs0 << 10 | ctrl_slave_ratio_cs0));
WR_MEM_32(CMD1_REG_PHY1_CTRL_SLAVE_RATIO_0,(ctrl_slave_ratio_cs0 << 10 | ctrl_slave_ratio_cs0));
WR_MEM_32(CMD2_REG_PHY1_CTRL_SLAVE_RATIO_0,(ctrl_slave_ratio_cs0 << 10 | ctrl_slave_ratio_cs0));
WR_MEM_32(CMD0_REG_PHY1_DLL_LOCK_DIFF_0,cmd_dll_lock_diff);
WR_MEM_32(CMD1_REG_PHY1_DLL_LOCK_DIFF_0,cmd_dll_lock_diff);
WR_MEM_32(CMD2_REG_PHY1_DLL_LOCK_DIFF_0,cmd_dll_lock_diff);
}
}
Emif0_MMR_Config(UWORD32 read_latency,UWORD32 tim1,UWORD32 tim2,UWORD32 tim3,UWORD32 ref_ctrl,UWORD32 sdram_config)
{
/*Program EMIF0 CFG Registers*/
WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1, read_latency);
WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1_SHADOW, read_latency);
WR_MEM_32(EMIF4_0_SDRAM_TIM_1, tim1);
WR_MEM_32(EMIF4_0_SDRAM_TIM_1_SHADOW, tim1);
WR_MEM_32(EMIF4_0_SDRAM_TIM_2, tim2);
WR_MEM_32(EMIF4_0_SDRAM_TIM_2_SHADOW, tim2);
WR_MEM_32(EMIF4_0_SDRAM_TIM_3, tim3);
WR_MEM_32(EMIF4_0_SDRAM_TIM_3_SHADOW, tim3);
WR_MEM_32(EMIF4_0_SDRAM_CONFIG, sdram_config);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x10000000|DDR3_EMIF_REF_CTRL_DEFINE1);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL_SHADOW, DDR3_EMIF_REF_CTRL_DEFINE1);
WR_MEM_32(EMIF4_0_SDRAM_ZQCR,DDR3_EMIF_SDRAM_ZQCR_DEFINE);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, DDR3_EMIF_REF_CTRL_DEFINE1);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL_SHADOW, DDR3_EMIF_REF_CTRL_DEFINE1);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, ref_ctrl);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL_SHADOW, ref_ctrl);
}
Emif1_MMR_Config(UWORD32 read_latency,UWORD32 tim1,UWORD32 tim2,UWORD32 tim3,UWORD32 ref_ctrl,UWORD32 sdram_config)
{
/*Program EMIF0 CFG Registers*/
WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1, read_latency);
WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1_SHADOW, read_latency);
WR_MEM_32(EMIF4_1_SDRAM_TIM_1, tim1);
WR_MEM_32(EMIF4_1_SDRAM_TIM_1_SHADOW, tim1);
WR_MEM_32(EMIF4_1_SDRAM_TIM_2, tim2);
WR_MEM_32(EMIF4_1_SDRAM_TIM_2_SHADOW, tim2);
WR_MEM_32(EMIF4_1_SDRAM_TIM_3, tim3);
WR_MEM_32(EMIF4_1_SDRAM_TIM_3_SHADOW, tim3);
WR_MEM_32(EMIF4_1_SDRAM_CONFIG, sdram_config);
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x10000000|DDR3_EMIF_REF_CTRL_DEFINE1);
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL_SHADOW, DDR3_EMIF_REF_CTRL_DEFINE1);
WR_MEM_32(EMIF4_1_SDRAM_ZQCR,DDR3_EMIF_SDRAM_ZQCR_DEFINE);
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, DDR3_EMIF_REF_CTRL_DEFINE1);
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL_SHADOW, DDR3_EMIF_REF_CTRL_DEFINE1);
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, ref_ctrl);
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL_SHADOW, ref_ctrl);
}
Emif_PRCM_Clk_Enable()
{
WR_MEM_32(CM_DEFAULT_FW_CLKCTRL, 0x2); /*Enable the EMIF FireWall Clocks*/
WR_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
WR_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL, 0x2); /*Enable EMIF0 Clock*/
WR_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL, 0x2); /*Enable EMIF1 Clock*/
WR_MEM_32(CM_DEFAULT_DMM_CLKCTRL, 0x2); /*Enable EMIF1 Clock*/
while((RD_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300)!=0x300); /*Poll for L3_FAST_GCLK & DDR_GCLK are active*/
while(RD_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL)!=0x2); /*Poll for Module is functional*/
while(RD_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL)!=0x2); /*Poll for Module is functional*/
while(RD_MEM_32(CM_DEFAULT_DMM_CLKCTRL)!=0x2); /*Poll for Module is functional*/
}
Vtp_Enable()
{
// Write 1 to ENABLE bit
WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000040 );
WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000040 );
// Write 0 to CLRZ bit
WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) & 0xfffffffe );
WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) & 0xfffffffe );
// Write 1 to CLRZ bit
WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000001 );
WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000001 );
// Read VTP control registers & check READY bits
while( (RD_MEM_32(VTP0_CTRL_REG) & 0x00000020) != 0x20);
while( (RD_MEM_32(VTP1_CTRL_REG) & 0x00000020) != 0x20);
}
/********************************************************************************
DDR Initialization and Configurations
*********************************************************************************/
menuitem "TIDM814x DDR Configuration"
hotmenu DDR2_EMIF0_EMIF1_333MHz_Config()
{
cmdDDRPLL(CLKIN,19,666, 2);
GEL_TextOut("\tDM814x DDR2 EVM EMIF0 and EMIF1 configuration in progress......... \n");
cmd_DDR2_EMIF0_EMIF1_Config(DDR2_PHY_0_RD_DQS_CS0_DEFINE,DDR2_PHY_0_WR_DQS_CS0_DEFINE,DDR2_PHY_0_RD_DQS_GATE_CS0_DEFINE,DDR2_PHY_0_WR_DATA_CS0_DEFINE,DDR2_PHY_1_RD_DQS_CS0_DEFINE,DDR2_PHY_1_WR_DQS_CS0_DEFINE,DDR2_PHY_1_RD_DQS_GATE_CS0_DEFINE,DDR2_PHY_1_WR_DATA_CS0_DEFINE,DDR2_EMIF_DDRPHYCR_DEFINE,DDR2_EMIF_TIM1_DEFINE,DDR2_EMIF_TIM2_DEFINE,DDR2_EMIF_TIM3_DEFINE,DDR2_EMIF_REF_CTRL_DEFINE,DDR2_EMIF_SDRAM_CONFIG_DEFINE);
GEL_TextOut("\tDM814x DDR2 EVM EMIF0 and EMIF1 configuration is DONE. \n");
}
hotmenu DDR2_EMIF0_EMIF1_400MHz_Config()
{
cmdDDRPLL(CLKIN,19,800, 2);
GEL_TextOut("\tDM814x DDR2 EVM EMIF0 and EMIF1 configuration in progress......... \n");
cmd_DDR2_EMIF0_EMIF1_Config(DDR2_PHY_0_RD_DQS_CS0_DEFINE,DDR2_PHY_0_WR_DQS_CS0_DEFINE,DDR2_PHY_0_RD_DQS_GATE_CS0_DEFINE,DDR2_PHY_0_WR_DATA_CS0_DEFINE,DDR2_PHY_1_RD_DQS_CS0_DEFINE,DDR2_PHY_1_WR_DQS_CS0_DEFINE,DDR2_PHY_1_RD_DQS_GATE_CS0_DEFINE,DDR2_PHY_1_WR_DATA_CS0_DEFINE,DDR2_EMIF_DDRPHYCR_DEFINE,DDR2_EMIF_TIM1_DEFINE,DDR2_EMIF_TIM2_DEFINE,DDR2_EMIF_TIM3_DEFINE,DDR2_EMIF_REF_CTRL_DEFINE,DDR2_EMIF_SDRAM_CONFIG_DEFINE);
GEL_TextOut("\tDM814x DDR2 EVM EMIF0 and EMIF1 configuration is DONE. \n");
}
hotmenu DDR3_EMIF0_EMIF1_300MHz_Config()
{
cmdDDRPLL(CLKIN,19,600, 2);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress......... \n");
cmd_DDR3_EMIF0_EMIF1_Config(DDR3_PHY_0_RD_DQS_CS0_DEFINE,DDR3_PHY_0_WR_DQS_CS0_DEFINE,DDR3_PHY_0_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_0_WR_DATA_CS0_DEFINE,DDR3_PHY_1_RD_DQS_CS0_DEFINE,DDR3_PHY_1_WR_DQS_CS0_DEFINE,DDR3_PHY_1_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_1_WR_DATA_CS0_DEFINE,DDR3_EMIF_DDRPHYCR_DEFINE_300,DDR3_EMIF_TIM1_DEFINE_300,DDR3_EMIF_TIM2_DEFINE_300,DDR3_EMIF_TIM3_DEFINE_300,DDR3_EMIF_REF_CTRL_DEFINE2_300,DDR3_EMIF_SDRAM_CONFIG_DEFINE_300);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. \n");
}
hotmenu DDR3_EMIF0_EMIF1_333MHz_Config()
{
cmdDDRPLL(CLKIN,19,666, 2);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress......... \n");
cmd_DDR3_EMIF0_EMIF1_Config(DDR3_PHY_0_RD_DQS_CS0_DEFINE,DDR3_PHY_0_WR_DQS_CS0_DEFINE,DDR3_PHY_0_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_0_WR_DATA_CS0_DEFINE,DDR3_PHY_1_RD_DQS_CS0_DEFINE,DDR3_PHY_1_WR_DQS_CS0_DEFINE,DDR3_PHY_1_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_1_WR_DATA_CS0_DEFINE,DDR3_EMIF_DDRPHYCR_DEFINE_333,DDR3_EMIF_TIM1_DEFINE_333,DDR3_EMIF_TIM2_DEFINE_333,DDR3_EMIF_TIM3_DEFINE_333,DDR3_EMIF_REF_CTRL_DEFINE2_333,DDR3_EMIF_SDRAM_CONFIG_DEFINE_333);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. \n");
}
hotmenu DDR3_EMIF0_EMIF1_400MHz_Config()
{
cmdDDRPLL(CLKIN,19,800, 2);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress......... \n");
cmd_DDR3_EMIF0_EMIF1_Config(DDR3_PHY_0_RD_DQS_CS0_DEFINE,DDR3_PHY_0_WR_DQS_CS0_DEFINE,DDR3_PHY_0_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_0_WR_DATA_CS0_DEFINE,DDR3_PHY_1_RD_DQS_CS0_DEFINE,DDR3_PHY_1_WR_DQS_CS0_DEFINE,DDR3_PHY_1_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_1_WR_DATA_CS0_DEFINE,DDR3_EMIF_DDRPHYCR_DEFINE_400,DDR3_EMIF_TIM1_DEFINE_400,DDR3_EMIF_TIM2_DEFINE_400,DDR3_EMIF_TIM3_DEFINE_400,DDR3_EMIF_REF_CTRL_DEFINE2_400,DDR3_EMIF_SDRAM_CONFIG_DEFINE_400);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. \n");
}
hotmenu DDR3_EMIF0_EMIF1_450MHz_Config()
{
cmdDDRPLL(CLKIN,19,900, 2);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress......... \n");
cmd_DDR3_EMIF0_EMIF1_Config(DDR3_PHY_0_RD_DQS_CS0_DEFINE,DDR3_PHY_0_WR_DQS_CS0_DEFINE,DDR3_PHY_0_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_0_WR_DATA_CS0_DEFINE,DDR3_PHY_1_RD_DQS_CS0_DEFINE,DDR3_PHY_1_WR_DQS_CS0_DEFINE,DDR3_PHY_1_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_1_WR_DATA_CS0_DEFINE,DDR3_EMIF_DDRPHYCR_DEFINE_450,DDR3_EMIF_TIM1_DEFINE_450,DDR3_EMIF_TIM2_DEFINE_450,DDR3_EMIF_TIM3_DEFINE_450,DDR3_EMIF_REF_CTRL_DEFINE2_450,DDR3_EMIF_SDRAM_CONFIG_DEFINE_450);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. \n");
}
hotmenu DDR3_EMIF0_EMIF1_533MHz_Config()
{
cmdDDRPLL(CLKIN,19,1066, 2);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress......... \n");
cmd_DDR3_EMIF0_EMIF1_Config(DDR3_PHY_0_RD_DQS_CS0_DEFINE,DDR3_PHY_0_WR_DQS_CS0_DEFINE,DDR3_PHY_0_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_0_WR_DATA_CS0_DEFINE,DDR3_PHY_1_RD_DQS_CS0_DEFINE,DDR3_PHY_1_WR_DQS_CS0_DEFINE,DDR3_PHY_1_RD_DQS_GATE_CS0_DEFINE,DDR3_PHY_1_WR_DATA_CS0_DEFINE,DDR3_EMIF_DDRPHYCR_DEFINE_533,DDR3_EMIF_TIM1_DEFINE_533,DDR3_EMIF_TIM2_DEFINE_533,DDR3_EMIF_TIM3_DEFINE_533,DDR3_EMIF_REF_CTRL_DEFINE2_533,DDR3_EMIF_SDRAM_CONFIG_DEFINE_533);
GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. \n");
}
/*************************************************************************************************/
with the hotmenue command DDR3_400 in CCS 4.2.5 to configure the DDR3 Controller.
Currently EMIF0 looks like it isn't accessible at all,but EMIF1 looks like it works. So we are concentrating on getting EMIF1 fully functional right now.
After executing the DDR3_400 config command, we execute a simple pattern program to check what happens at certain memory locations (read=written?,...)
What we observe is that every 4KiB we get a mirror effect (e.g. val @0x80000000 = val 0x80001000, val @0x80002000 = val 0x80003000,...).
At the moment we're stuck at this point, but we think our register configurations are correct or I least we couldn't find an error in those.
We use the following RAM: MT41J128M16-125 (Micron).
0513.Micron_2Gb_DDR3_SDRAM.pdf
Thanks in advance for your ideas and suggestions.
Regards, Markus
