TMDXEVM6678LE Access FPGA registers

Anthony Diak

I'm trying to update some FPGA configuration registers. I've found the addresses for the registers in http://wfcache.advantech.com/support/TMDXEVM6678L_Technical_Reference_Manual_2V00.pdf

Is there something special I need to do before changing these values? I've tried connecting with the probe, running the GEL file to initialize everything/map memory, and then changing the values via the memory browser for a quick test. This doesn't seem to work.

I'm most interested in changing the clock source (SPI + 0x50), but for a sanity check I'm trying to control the debug LEDs (SPI + 0x8, bits 3-0). For the SPI base address I'm using 0x20BF0000 as the base address (as defined in the tech reference manual).

I've also tried changing the LEDs via a program, and that didn't seem to work either:

    unsigned char mask[2] = {0xAA, 0x55};
    int i = 0;
    while (1)
    {
      Task_sleep(100);

      *(volatile unsigned char*)(CSL_SPI_BASE + 0x8) = mask[i];

      if (++i > 1) i=0;
    }

over 13 years ago

0 Anthony Diak over 13 years ago

Intellectual 430 points

I've figured it out by looking at some code in the IBL. I had to do some SPI protocol stuff. Here's what I ended up with. Now I have blinking LEDs!

#define DEVICE_REG32_W(x,y)   *(volatile unsigned int *)(x)=(y)
#define DEVICE_REG32_R(x)    (*(volatile unsigned int *)(x))
#define FPGA_WRITE_REG_CMD(addr,byte)       (((addr & 0x7f) << 8) | (byte & 0xff))
#define FPGA_ICS557_SEL_CTRL_REG    0x50 /* ICS 557 Clock Selection Control Register*/
#define FPGA_LED_REG    0x8 /* ICS 557 Clock Selection Control Register*/
#define DEVICE_SPI_BASE(x)          0x20bf0000u
#define DEVICE_SPI_MOD_DIVIDER      6
#define DEVICE_SPI_MAX_DIVIDER      0xff
#define SPI_REG_SPIGCR0         0x00
#define SPI_REG_SPIGCR1         0x04
#define SPI_REG_SPIFLG          0x10
#define SPI_REG_SPIPC0          0x14
#define SPI_REG_SPIDAT0         0x38
#define SPI_REG_SPIDAT1         0x3c
#define SPI_REG_SPIBUF          0x40
#define SPI_REG_SPIDELAY        0x48
#define SPI_REG_SPIFMT(x)       (0x50 + ((x)*4))
/* Register values */
#define SPI_REG_VAL_SPIGCR0_RESET           0x0
#define SPI_REG_VAL_SPIGCR0_ENABLE          0x1

void setLEDs(unsigned char value)
{
    /* Reset SPI */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);

    /* Release Reset */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_ENABLE);

    /* CS1, CLK, in and out are functional pins, FPGA uses SPI CS1 */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIPC0, 0xe02);

    /* prescale=7, char len=16 */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIFMT(0), 0x710);

    /* C2TDELAY=0x6, T2CDELAY=0x3 */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIDELAY, 0x6030000);

    /* Master mode, enable SPI */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR1, 0x01000003);

    /* Write ICS 557 Clock Selection Control Register in the FPGA */
    /* 1 : FPGA_ICS557_SEL s driven high */
    DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0,
                   FPGA_WRITE_REG_CMD(FPGA_LED_REG,value));
    chipDelay32(10000);
    /* Reset SPI */
    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
}

/*
* ======== taskFxn ========
*/
Void taskFxn(UArg a0, UArg a1)
{
    System_printf("enter taskFxn()\n");

    unsigned char mask[2] = {0xAA, 0x55};
    int i = 0;
    while (1)
    {
      Task_sleep(100);

      setLEDs(mask[i]);

      if (++i > 1) i=0;
    }

    System_printf("exit taskFxn()\n");
}

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TMDXEVM6678LE Access FPGA registers