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SRIO retry-stopped error

dp
Intellectual 990 points

We're tesing c6678 to communicate with lattice fpga via srio. But encounter some error.

The FPGA could send NWRITE c6678 dozens of packets successfuly, and may stop for a while about 450ms, then continue send. 

we use DIO mode, and the c6678 does nothing except ready for receiving.

While receiving, the SP0_ERR_STAT of C6678 is 0x00020602, which means: Input Error-encountered and Input Retry-stopped.

What I want to know is :

1. what situations will  result in this error?

2. What the use of flow control ?

3. How to config srio to work at 1.25G?  

  • 0
    TI__Prodigy 230 points

    Hi,

    1. You may receive input error-encountered for a variety of reasons (link misalignment, unexpected symbols received, etc...). If you are in the input error encountered state the port will still automatically try to recover, but when you are in the input-error stopped state you must manually perform a reset or resyncrhonization procedure. The various errors are all listed in the documentation.

    2. Flow control allows certain transmit queues to be left out of scheduling and also allows you to set up filter parameters for various SRIO flows based on DESTID. Please see section 2.3.7 of user's guide for detailed information. Keep in mind this is not the same as the RX flow mapping which assigns receive queue mapping schemes to certain priority levels.

    3. If you will please refer to table 2-5, Frequency Range versus MPY Value, you will see that you can use a combination of eighth rate, 16 MPY, and 156.25MHz to achieve a desired line rate of 1.25 GHz.

    Please let me know if there is anything not mentioned or ambiguous in the documentation you would like some clarity on.

    Regards,

    Sahil

  • 0 in reply to Sahil Hingorani
    Intellectual 990 points

    Thanks Sahil.

    We use FPGA write DSP in DIO mode, and it cannot nwrite persistently in the rate of 1x3.125G, 1x2.5G, and 4x1.25G. Only write well in 1x 1.25G. 

    By observing the value of SP0_ERR_STAT, we think it would be physical link error. As you say, it may be link misalignment, unexpected symbols received, etc. But what I want to know is the real reason of these errors. Are there any electrical requirments that not satisfied ? What should I do to adjust the register of C6678 or FPGA to achieve good performance?

  • 0 in reply to dp
    Intellectual 990 points

    FPGA nwrites C6678 at 1x1.25G, and could send sustained data successfully.

    But in 4x1.25G mode, FPGA nwrite C6678 dozens of packets, then stop for about 430ms, then continue transfer dozens of packets and stop for 430ms, again and again. The wave form captured by oscilloscope as follows: