May be in the SD controller of C5504/05, and cause an error when you issue the multiple data read command(CMD18).
After issuing a CMD18, I have been monitoring the bit of DRRDY, may this bit is not set.
The documentation for the SD controller when you issue the commands that the command response, it was decided to confirm the response command.
I added that code, the error no longer occurs.
However, because the only code was added to reference the same register status, resolution and root cause is not considered.
Code image
while (!RSPDNE); // add
while (!DRRDY);
MMCST0:RSPDNE( bit2 )
MMCST0:DRRDY( bit10 )
Considered even though the data is in the FIFO when an error has occurred DRRDY is not set, DRFUL and FIFOFUL of MMCST1 and because it is set.
Q1
Has been set to FIFOFUL and DRFUL, is set DRRDY is not?
Q2
Timing from the FIFO into the DRR shifter?