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OMAP 4460's GPMC interface with dual port SRAM

dennis Dominic
Prodigy 120 points

Hi all,

I am not familiar with SRAM interface, where can I finds more application notes/guide on how to use OMAP4460's GPMC (from Panda board expansion port)?

My intention is  to be able interface with a DUAL port SRAM.

Current I found 2 company making that, IDT(IDT7006S/L) & Cypress(CY7C008V,CY7C018V&etc), so these 2 will be my target.

For IDT, they have a 14bit address bus & 8 bit data bus.

For Cypress, 16 bits address bus & 8 bit data bus.

From OMAP4430 datasheet's, pages 3148 there is 2 very brief example /condition how GPMC to connect multiplexed & non multiplexed memory devices.

Since my targeted product is 14bit & 16 bit address, I assume I need go to the option 1, multiplexed.

My current thinking, I need to have another multiplexed device on between the OMAP & my dual port sram. Is this correct? Since my ext device is not a multiplexed memory.

If there is another multiplexer in between, how my firmware need to be setup?

Thanks

  • 0
    Prodigy 120 points

    is it possible/allow to do like the following ?

    1. Address pin [0:15] convert to data pin: [0:7], so we have left address pin [8:15](8pins)
    2. Convert the leftover address pin [8:15](8pins) remap it as address pin[0:8]
    3. Then address pin[17:23] remap it to serves as address pin[9:16]?

  • 0 in reply to dennis Dominic
    Prodigy 120 points

    any guys from TI can help out on this matter?

  • 0 in reply to dennis Dominic
    TI__Prodigy 460 points

    Looking at OMAP4430 Public TRM vAE, section 15.4, sh 3143, General Purpose Memory Controller;

    Yes, you will need a CPLD in between to separate the address and data lines from AD[15..0] (also connect all control lines and clk, even if only in pass through mode, to keep timing the same).  Since you need 16bit address, use figure 15-50, Multiplexed Address/Data 16bit device, using D[7..0] (do not use D[8..15], or fix to 1 in the CPLD)   Note that the address lines (see Table 15-215) start at A1, not A0, because it assumes a two byte data, instead of one, so only even addresses would be valid with your 8 bit data bus D[7..0].  Also, note the comments after Table 15-215 about register settings for the different configurations.

    As for actually having CPLD code for this, TI does not provide this. 

    Kind regards,

  • 0 in reply to dennis Dominic
    TI__Expert 5515 points

    Hi Dennis,

    As you mentioned you will need to use the multiplexed mode because the number of lines (16).

    So what you can do is to use lines A[1:16] to address and then mux to data lines and use d[0:7] since you only need 8 bits.

    But you don't need anything else between omap and your dual SRAMs because you also have the option to use the CS (Chip Select) pins, in that way you can choose to read/write from one SRAM or the other.

  • 0 in reply to Israel Cepeda
    TI__Guru 64450 points

    There is an example of this type of implementation on the following wiki article.  Although the article is centered around a different device, the concept is the same.

    Look for the illustration entitled "16-bit NOR with external latch".

    Using a SN74ALVCH16374 as an address latch will simplify the design from a CPLD implementation.

    Review Table 15-216 in the OMAP4430 Technical Reference Manual to know which signals to use for the latch.