Hi,
The DM8148 specification allows for two DDR3 devices to be physically mirrored with one component on the CS and the other on the PS. According to JEDEC standards for DDR3 devices it is possible configure the DDR3 so that some address pins are mirrored allowing for easier routing by avoiding the crossing of signal traces. However, I don't see any discussion of how this is supported on the DSP. The only thing that is talked about is mirroring is supported but now specifically how it is supported in the DDR3 controller itself.
Our board layout has been stopped on this issue. Can you please provide detailed information regarding this issue.
Many Thanks
Michael Stamler
CEO, Xicore Technologies Ltd.
www.xicore.net