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SATA PLL Config Registers

REHAN KHAN
Prodigy 100 points

Hi,

I want to set the SATA PLL CONFIG REGISTERS. But i cant able to modify the register values. In Reference document it is written that there is a lock bit which protects writing of this registers. I didn't find this lock bit in the document. where it is mentioned please tell me. I want to modify the register values for 100mhz clock.

Best Regards,

Rehan Khan

  • 0
    TI__Expert 7225 points

    Hi Rehan,

    Can you please share more details? Please share the known issue you have seen. I cannot locate that. 

    Also is this for the PCIe registers or the PLL registers that we need to look for? 

    KIndly provide as many details as possible.

    Thanks 

    Best Regards

    Feroz

  • 0 in reply to K Md Feroz Irfan
    Prodigy 100 points

    Hi,

    We are some problem in sata. we have followed the workaround given in the release notes.

    SATA read/write issues due to internal 20MHz clock.

    The workaround is to either use 100MHz external clock from PCI. or 20MHz clock source on the board.

    what we have seen in the DM8148 EVM Schematic there is clock generator IC CDCM61002RHBR. which is same in our board also. It gives 100 MHz clock to SERDES differential clock input. Now I want to configure the sata pll config register according to this. so i want to change the SATA_PLL_CONFIG register to take 100 MHz clock reference while in source code it is made for 20 MHz clock. This what we understand to solve the sata read/write issue.

    Please correct us if we are doing anything wrong and suggest correct method to achieve this.

    Best Regards,

    Rehan Khan.

  • 0 in reply to REHAN KHAN
    TI__Guru**** 170625 points

    hi Rehan,

    The lock bit mentioned in the TRM is actually lock register - MMR_LOCK1 (at address 0x48140064). You have to write the value of 0xF757FDC0 in the MMR_LOCK1[31:0] to UNLOCK the writing for all registers in the range 0x0600 - 0x07FF. Consider this range as offsets. Thus the SATA_PLLCFG0 register (offset 0x0720, base address 0x48140720) can be written, and bit [31] SEL_IN_FREQ can be cleared to 0x0 (100MHz).

    best regards,

    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 95 points

    Hi REHAN,

    I have some problems in SATA, and want to use 100MHz external clock just like you do.
    Have you successed to use 100MHz instead of 20MHz on your board?

    According to TRM(sprugz8a.pdf), I know there's a register SATA_PLLCFG0, bit[31] SEL_IN_FREQ
    can do this clock changing.

    But should I also modify the register PCIE_PLLCFG0/1/2/3/4,
    cause there's a message in the description.

    This is connected to "CF_APLL_0" on SERDES ANA Initial Settings required prior to power up sequence:
    PCIE_100M: 4000 7000 ; SATA_20M: C000 7060 ; SATA_100M: 4000 7060

    Could you give me some hint to change SATA input frequency?
    Thank you.

    Best Regards,

    Hong

  • 0 in reply to Hong0820
    TI__Guru**** 170625 points

    hi Hong,

    Do you succeed to change the SATA input frequency to 100MHz?

    Please have a look on TRM, Figure 2-9. SERDES and Ethernet Clock Structure. You will see that the initial 100MHz clock signal is going first to the PCIE PLL, and after that to the SATA PLL. In PCIE_PLLCFG0[31] SEL_IN_FREQ bit, you can select the 100MHz clock (it is selected by default). And this should be enough for the SATA PLL 100MHz clock input.

    Best regards,

    Pavel