Problem of EMIFA write address

Pei Luo

I have a problem of EMIFA, I write 90 data into EMIFA_CE5 area and capture the address using Chipscope. The assress shown in Chipscope is different from I set.

I set the address and write the data as following:

#define EMIFA_CE5_BASE_ADDR (0xd0000060u)

volatile long long *pSyncData = (volatile long long *)EMIFA_CE5_BASE_ADDR;

EMIFA_CONFIGREG_STAT &= ~(0x80000000); //config emifa work in little endian mode

EMIFA_CONFIGREG_CE4CFG = 0x8000030b; //emifa works in sysnc mode; read letance =2; 64bits wide;

EMIFA_CONFIGREG_CE5CFG = 0x80000107; //emifa works in sysnc mode; read letance =2; 64bits wide

I write 90 data to EMIFA area as the following:

for (index = 0; index < 90; index++)

{

SyncData[index] = 0x1234567812345678;

}

The address should begin from 0xd0000060u, but the address in Chipscope is as following:

Here is my question, the address is so different from my settings, why?

over 13 years ago

0 RandyP over 13 years ago

TI__Guru* 84110 points

Pei Luo,

You have what appear to be serious sample-rate problems with your Chipscope time units relative to the DSP signal rates. What are the rates for the EMIFA clock and the DSP_FPGA_CLK, and the Chipscope rate?

Your EMIFA_ADDR lines look like they are incrementing just the way you want them to. What did you expect to be on these lines? Please check how the FPGA EMIFA_ADDR signals are connected to the DSP and how the DSP's EMIFA uses its address lines for the configuration that you are using. The EMIFA User's Guide may be of help for you here. Please let us know if you are unable to locate the address line mapping information.

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click Verify Answer , below.

0 Pei Luo over 13 years ago in reply to RandyP

Prodigy 80 points

Thank you for your reply and I think I should clarify my question at first.

As you can see that I set my EMIFA write address begin from 0xd0000060u, and I connect my low 8 bits to Chipscope. The address[7:0] should begin from 0x60, but now the initial address is from 0x0c. The increment and number of adress are right, but the initial address is not correct as shown in the Chipscope.

So, what may be the problem? Thank you!

0 RandyP over 13 years ago in reply to Pei Luo

TI__Guru* 84110 points

Pei Luo,

What you have clarified is not what you are actually doing on your board.

RandyP said:
Please check how the FPGA EMIFA_ADDR signals are connected to the DSP and how the DSP's EMIFA uses its address lines for the configuration that you are using. The EMIFA User's Guide may be of help for you here. Please let us know if you are unable to locate the address line mapping information.

Bit 0 of the FPGA's EMIFA_ADDR[7:0] is connected to which pin on the DSP?

Which internal address bit of the DSP's 32-bit address bus is this pin connected to?

Please note that the answer to this question would be different if you were using a different EMIFA configuration. So you must find a conversion table in the EMIFA User's Guide to tell you how to design this interconnection, or how to interpret this interconnection.

If you do not understand what I am talking about, please look at the EMIFA User's Guide to help you understand addressing for the EMIFA.

Regards,
RandyP

0 Pei Luo over 13 years ago in reply to RandyP

Prodigy 80 points

Thank you very much, I have made such a stupid mistake!

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Problem of EMIFA write address