Output 25Mhz RMII1_REFCLK

Keldy

Expert 1835 points

Hi,

Can RMII1_REFCLK output 25Mhz clock at u-boot level ?

Thanks & Regards

Keldy

over 13 years ago

0 Anil over 13 years ago

TI__Expert 6655 points

Hi Keldy,

What is your use-case?

We can modify PLL configurations (M5) to get the RMII clock as 25MHz, but some of the other clocks get affected like CPTS, remaining MII clocks. Details can be found from TRM section "8.1.1.6.6 Core PLL Description"

Regards

AnilKumar

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0 Keldy over 13 years ago in reply to Anil

Expert 1835 points

Hi AnilKumar,

my use-case is i want to enable ethenet at u-boot, but my custom board will use RMII1_REFCLK as clock for ethernet PHY.

can i use the u-boot.img come from the AM335x EVM ? the AM335x EVM use externel crystal as clock for PHY, so any changes needed to the u-boot code?

Thanks & Regards

Keldy

0 Anil over 13 years ago in reply to Keldy

TI__Expert 6655 points

Keldy said:

can i use the u-boot.img come from the AM335x EVM ? the AM335x EVM use externel crystal as clock for PHY, so any changes needed to the u-boot code?

The only option you have is changing the u-boot code for writing the new HS-DIVIDER value (16 instead of 8).

You have to change macro in the u-boot for getting "MHZ_50_CLK" as 25MHz instead of 50.

these clocks will get effected, if you change the rate to 125MHz (dependent clock details can be found in TRM, core dpll)

core_clkoutm5 = 125MHz

cpts_ref_clk = 125MHz

mhz_250_clk = 125MHz

mhz_125_clk = 67.5MHz

mhz_50_clk = 25MHz (which meets your requirement)

mhz_5_clk = 12.5MHz

Along with 25MHz clock, if you require defalut rates on any one of the above clocks, then it won't possible.

Regards

AnilKumar

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0 Keldy over 13 years ago in reply to Anil

Expert 1835 points

Hi AniKumar,

Thanks your advise,

i want to ask where is the file location and what is the file name that i can change the HS-DIVIDER value?

Thanks & Regards

Keldy.

0 Anil over 13 years ago in reply to Keldy

TI__Expert 6655 points

Hi Keldy,

Code is present at (board/ti/am335x/pll.c, core_pll_config()), this file using the macro defined in the header file.

Modifications required in "arch/arm/include/asm/arch-ti81xx/clocks_am335x.h" file

Replace #define COREPLL_M5 8 with #define COREPLL_M5 16

Regards

AnilKumar

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0 Keldy over 13 years ago in reply to Anil

Expert 1835 points

Hi AnilKumar,

Thanks for reply.

no clock coming out from RMII1_REFCLK. how to enable the RMII1_REFCLK ?

is the u-boot code will enable the RMII1_REFCLK to output clock by default ?

Thanks & Regards

Keldy

0 Keldy over 13 years ago in reply to Keldy

Expert 1835 points

Hi AnilKumar,

Think i can enable RMII_REFCLK by setting the register GMII_SEL.rmii1_io_clk_en. But as you said, configure RMII_REFCLK will affect other clock.

My objective is provide 25Mhz clock to gigabit ethernet PHY instead of using external 25Mhz crystal.

From your opinion, do you think i can use CLKOUT2 instead of RMII_REFCLK ?

will it have any differences between using CLKOUT2, RMII1_REFCLK, or external crystal as 25Mhz clock source?

Thanks & Regards

Keldy

0 Anil over 13 years ago in reply to Keldy

TI__Expert 6655 points

Hi Keldy,

Can you check the pinmux settings of "conf_rmii1_refclk" pin is configured for rmii or some other. Section "9.3.1.50" in TRM

In your case you should use this pin as RMII

Regards

AnilKumar

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Output 25Mhz RMII1_REFCLK