I'm trying to get McASP3 running on a DM8148 device without any success. McASP3 is configured to use an external Tx frame sync and external Tx clock. I use two serializers – SER0 for transmit and SER1 for receive. The receive section runs off the transmit clock and frame sync signals (i.e., synchronous mode).
The device attached to McASP3 provides an 8 kHz Frame sync signal, 1-bit wide, and the clock signal runs at 520 kHz, thus there are 65 clock bits per frame. The device sources the Tx framesync and Tx clock signals.
The driver configuration sets up McASP3 to operate in TDM mode with two 16-bit timeslots.
I’ve verified the pin-mux registers for McASP3 are configured to enable McASP3 functions and the module is powered-up:CM_ALWON_MCASP_3_4_5_CLKCTRL is set to 2. PFUNC and PDIR McASP registers are also setup appropriately.
I’ve polled the ACLKX and AFSR pins of the PDIN register for a 1-ms period and verified that the clock and framesync signals are present and changing at the correct rates.
The McASP driver that programs McASP3 runs on the DSP-side of the 8148. I’ve been using it successfully to setup McASP2, which is connected to an AIC3104 audio codec running in I2S mode, with two 16-bit timeslots per frame. The AIC3104 sources the Tx framesync and Tx clock signals.
I can provide more information about register settings and McASP configuration, but before doing that, I’d like to know if you aware of any reason why the McASP would not operate correctly if there are 65 clocks per frame.