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about srio loopback

haopeng han
Expert 1120 points


Hi

I am debugging sRIO between c6678 and Altera SIV FPGA. Has anyone ever done this before?  I have some troubles in doing this.

I was wondering can the sRIO SerDes in DSP provide a loopback function to its partner, i.e. the FPGA sees the RX and TX signals shorted in the DSP side?

Thank you!

Han

  • 0
    TI__Genius 9915 points

    I am not sure that I understand what you are asking. We have SRIO loopback code in the PDK. But this is only to loop the TX from DSP to RX of the DSP.

    Thanks,

    Arun.

  • 0 in reply to ArunMani
    TI__Intellectual 2415 points

    Hi Han & Arun,

    The keystone SRIO HW has a line loopback feature, which can be used to loopback from DSP SRIO RX to TX (FPGA TX --> DSP RX --> line loopback --> DSP TX --> FPGA RX). To enable SRIO line loopback set PLM_SP(n)_IMP_SPEC_CTL.LLB_EN to '1'. For SRIO line loopback to work successfully the SRIO SERDES should be properly configured.

  • 0 in reply to Karthik Ramana Sankar
    Expert 1120 points

    Hi Karthik & Arun,

    Thank you for your info. Line loopback is what I wanted.

    The DSP on my board is a silicon revision 1.0, the SRIO SerDes loopback test does not function properly.  Could line loopback work normally on this silicon version? If ok, what else I need to configure besides PLM_SP(n)_IMP_SPEC_CTL.LLB_EN,  base on my SerDes loopback app?  Thank you!

    B.R.

    Han

  • 0 in reply to haopeng han
    TI__Intellectual 2415 points

    Hi Han,

    SRIO line loopback works correctly on revision 1.0 silicon. Please, check rev 1.0 silicon errata (C6678 errata), there is one errata related to SRIO line loopback (Advisory 17— Corruption of Contro l Characters In SRIO Line Loopback Mode Issue). Please, make sure you workaround this errata. No other configuration besides the PLM_SP(n)_IMP_SPEC_CTL.LLB_EN is required.

  • 0 in reply to haopeng han
    Intellectual 990 points

    Hi, Haopeng

    I'm debuging srio between fpga and dsp.

    Could you give me an contact to discuss ? 

    mine: dpinglee@163.com

    Regards,

    dp 

  • 0 in reply to dp
    Prodigy 170 points

    We are looking to set up the same type of loop back here. FPGA is an Altera Stratix IV and we are using the TI C6678 eval module...  Have you had any luck?  What example did you start from?  Any help would be appreciated...

    Thanks,

    Jonathan