Asynchronous Reads with Wait on EMIF

Derick Voegeli

I am having a problem in getting the L138 EMIF bus to hold a cycle until wait is removed. I am working on a AVNET spartan 6/OMAP L138 eval board, which uses CS2. The bus cycle completes while EMIF_WAIT is still asserted. All the other signals seem correct and the data does get to the bus within the wait time period, but the EMIF has already closed the transaction. I believe that I have the registers setup correctly, but I seem to be missing something. Would anyone be able to see what I have setup wrong.

Registers:

AWCC = 0xF0000080

CE2CFG = 0x483441AD

Thanks

over 14 years ago

0 Mukul Bhatnagar over 14 years ago

TI__Guru* 86105 points

Please make sure that

1) Wait is enabled

2) Wait assertion before the end of the strobe period is meeting the datasheet setup requirement

3) Programmed maximum wait time is not being exceeded.

Regards

Mukul

0 Ignacio Linares over 14 years ago in reply to Mukul Bhatnagar

Expert 1655 points

Mukul,

See attached waveforms. After the changes to the CE2CFG register was made, the emif_oe_n signal now extends 8 clock cycles past the deassertion of emif_wait1. We need the cycle to terminate upon deassertion of emif_wait1. There is still something not quite right. We have changed the value of R_HOLD (bits 6, 5, 4 in CE2CFG register) and it doesn't seem to affect the emif_oe_n signal.

7776.waveforms.docx

0 jc-ti over 14 years ago in reply to Ignacio Linares

TI__Mastermind 27585 points

In both the waveforms you attached here and sent in separate emails, the label for the CS used is "emif_cs3_n". Is it labeled incorrectly, or is the device actually hooked up to CS3?

If so, from the register settings CS3 isn't set up to use extended waits. This would also explain why changing R_HOLD has no effect.

Jeff

0 Derick Voegeli over 14 years ago in reply to jc-ti

Prodigy 40 points

Sorry for the confusion, but yes the label is incorrect. The real system will be using CS3, but on the eval board that I am using for testing, CS2 was the one that was connected, I didn't take the time to change the labels.

0 jc-ti over 14 years ago in reply to Ignacio Linares

TI__Mastermind 27585 points

What changes to the CE2CFG were made? Can you give the current value of the register now?

Changing the R_HOLD bits should directly affect how long the OE is held low after WAIT is deasserted. Even if you set R_HOLD to 0, you still see 8 cycles delay?

Jeff

0 Derick Voegeli over 14 years ago in reply to jc-ti

Prodigy 40 points

The value that goes in by default is 0x483441AD. After that I set the R_STROBE to 0x5 (first plot) or a value of 0x483442AD, and then I set R_STROBE to 0x6 or a value 0x4834432D for the second plot.

0 jc-ti over 14 years ago in reply to Derick Voegeli

TI__Mastermind 27585 points

If you change R_HOLD to 0 are you seeing the OE go high sooner after WAIT1 goes low?

Jeff

0 Derick Voegeli over 14 years ago in reply to jc-ti

Prodigy 40 points

I believe that the captures actually had R_HOLD either at zero or one. I am a bit stuck becuase the transceiver between the OMAP and the FPGA died, and I am waiting on replacement parts, so I can't retest at the moment. I do remember minimizing R_HOLD as much as possible.

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Asynchronous Reads with Wait on EMIF