Ethernet PHY connection and configuration

The KSZ9021RL data sheet says RX_ER, COL, and CRS should not be connected.  I agree as they are not required for RMII.

AM335x pin multiplexing for the first 12 pins in your list must be configured to operate in Mode 2 and the next 2 pins in your list must be configured to operate in Mode 0.

The KSZ9021RL device must be configured to operate in one of the four RMII mode selected by the MODE[3:0] inputs which are shared with the RXD[3:0] outputs.  These pins are connected to the AM335x GMII_RXD[3:0] pins which have week internal pull-down resistors turned on until software turns then off.  So the external strapping resistors used to select the KSZ9021RL mode of operation may need to over-drive the AM335x internal resistors.  You may want to consider connecting a AM335x GPIO pin that is pulled low during and after reset to the KSZ9021RL RESET_N input such that it will hold the KSZ9021RL in reset until software has turned off the internal pull-down resistors on the GMII_RXD[3:0] pins.  This may allow you to use higher impedance strapping resistors to select the KSZ9021RL mode of operation.

The AM335x I/Os supports 1.8 volt or 3.3 volt LVCMOS logic levels and the KSZ9021RL I/Os support 2.5 volt or 3.3 volt logic levels.  So both devices must have their respective I/O supplies configured to operate at 3.3 volts which is a common operating point.

Regards,
Paul

Hi Paul,

for your info, i'm using the RGMII interface. From the KSZ9021RL datasheet, the TX_ER, RX_ER, CRS, COL should not be connected.

how about the CLK125_NDO ? do i need to feed 125Mhz reference clock to AM335x_GMII1_REFCLK ?

how about the INT_N ? should be connected to somewhere else ?

from the AM335x EVM schematics, AM335x_GMII1_COL is connected to ETH_INTn (Atheros AR8031_AL1A), do i need to connect INT_N (KSZ9021RL) to AM335x_GMII1_COL ?

Thanks & Regards

Keldy

You can connect the INT_N output from the KSZ9021RL to AM335x if your Ethernet driver software expects interrupts from the PHY.

I assume the AM335x EVM designer connected the INT_N output to the GMII1_COL pin with plans to route the interrupt through the GPIO module which allows GPIO inputs to operate as interrupt inputs.  This would allow the NMIn interrupt input to be used for other functions.

I recommend you determine if your Ethernet software requires the interrupt input function.  If it does, then you should determine which AM335x interrupt inputs are supported by the software.  All pins configured as GPIO have the ability to be configured as interrupt inputs so you can connect the INT_N output to any GPIO pin or the NMIn pin.

Note: If you plan to use the NMIn pin, read the AM3335x silicon errata advisory that describes how the NMIn pin is active high in silicon revision 1.0.  This input will be changed to active low in the next silicon revision so you should provide a PCB option to route this signal through an inverter when using silicon revision 1.0 devices and bypass the inverter when using the newer revision devices.

You do not need to provide a 125MHz reference clock to AM335x.  The only signals you need are the first 14 in your original list.

The receive data is transferred with respect to the receive clock and the transmit data is transferred with respect to the transmit clock. You need to insure all timing parameters of both devices are within the specified operating range.  This may require timing adjustments via the KSZ9021RL RGMII Clock and Control Pad Skew and RGMII RX Data Pad Skew registers.  Many 1000Mbps Ethernet PHY provide a way to adjust RGMII signal timing and in most cases the method used to adjust timing is implement differently in every PHY.  So your Ethernet driver software will need to account for the specific method used by the KSZ9021RL.

Regards,
Paul

Hi Paul,

In my current board, the RX_ER, COL, and CRS were connected to the AM335x. will it be any concern if i dont remove it ? will it cause my RGMII interface fail ?

for your info, the ethernet in my design can't function, not sure whether is a hardware connection problem, or software driver problem.

Thanks & Regards,

Keldy

These pins will default to GPIO inputs while AM335x is held in reset and will remain GPIO inputs after reset if software does not reconfigure them.  This includes the ROM code, any boot loaders, the OS, or any application code.

You need to determine if any of the four possible ROM boot modes selected by your configuration of the SYSBOOT[4:0] inputs will attempt to drive these pins.  Most of the SYSBOOT[4:0] configuration options support a sequence of four ROM boot options.  If the first boot option in the sequence fails, the ROM code will attempt to boot from the next boot option in the sequence until all boot options are attempted.  For more information refer to the AM335x TRM.

You can leave them connected if your configuration of the SYSBOOT[4:0] inputs never selects a ROM boot option that drive these pins and these pins are not required for one of the other peripherals that can be pin multiplexed to these pins.

The safe approach would be to disconnect them.

Regards,
Paul

Hi Paul,

Regarding the ethernet software configuration, i found a micrel PHY driver in AM335x EVM SDK ("board-support/u-boot-2011.09-psp04.06.00.02/drivers/net/phy/micrel.c"),  

how i enable this micrel driver in u-boot?

and how i disable the previous PHY (AR8031_AL1A) driver ?

Thanks & Regards

Keldy

Hi Paul,

Would it be any concern if i connect micrel PHY RESET_N pin to AM335x WARMRST ,or PWRONRST, or RTC_PWRONRST ?

Thanks & Regards

Keldy

I can not think of any reason you should connect it to RTC_PWRONRSTn.  This input is only used to reset the AM335x RTC logic and should only go active the very first time power is applied to the device.

One option is to connect it to RWRONRSTn.  This is the reset input for the remaining AM335x logic and should be sourced by the power management IC (PMIC) or supervisor circuit that holds this signal low until all power supplies are valid.  This reset should go active the first time power is applied and anytime the device is powered back up after being in deep sleep.  This signal could also be used to reset the Ethernet PHY if powered up at the same time.

Connecting it to WARMRSTn may be an option, but you should review the TRM description to determine if the function of this pin meets your system requirements.

As mentioned previously in this post, you need to make sure the AM335x internal pull-up/pull-down resistors connected to the Ethernet PHY RXD[3:0] pins do not interfere with the external pull-up/pull-down resistors required to select the KSZ9021RL mode of operation.  The safest approach is to connect the Ethernet PHY reset to a GPIO pin with a default pull-down resistor that could be driven high by software after you know the respective internal resistors have been turned off.

Regards,
Paul

5557.RP_AM335x_w_eth.datHello,

I was reading through this post and wanted to ask you guys couple of question. I too would like to use a different PHY for ethernet, in my case since I'm only using it for debug purposes during development, I'm satisfied with 10/100 PHY - I picked the DP83848I since I've used this one before.

The questions I have are as follows:

1. Based on one of the replies in this thread, I should be able to leave the PHY in it's default mode (MII mode). This means I do not need any strap resistors, is this correct?

2. In this case, do I need the REFCLK signal to be connected to the processor (AM3352)? The reason I ask this is 2 fold,

a. The EVM, uses the REFCLK along with the other MII signals, (attached pdf) but when I select the pins using the IO Set within pin mux utility REFCLK is not selected and if I select it manually  it gives me IO Set Violation (correctly so)

b. The TRM mentions the REFCLK signal only in the RMII interface.

I've also attached my pin mux .dat file for reference. The PHY is http://www.ti.com/lit/ds/symlink/dp83848i.pdf

Please do let me know if my question is valid :)

Thank you

Regards

Santhosh

You can configure AM335x and DP83848 to operate in MII or RMII mode.  It sounds like you already know the AM335x pin mux tool should be used to to determine AM335x pin assignments.

You will need to follow the DP83848 documentation to determine how it should be configured for your design.  It looks like the MII_MODE(RX_DV) and SNI_MODE(TXD_3) pins need to be pulled to 0/x for MII mode, 1/0 for RMII mode, and 1/1 for SNI mode (SNI mode is not supported by AM335x).  You may need to determine the state of internal AM335x pull-up/pull-down resistors connected to these signals while DP83848 samples these boot strap inputs.  It may be necessary to add external resistors that over-drive the AM335x internal resistors is there are pulling the DP83848 input to the wrong state.

 The REFCLK is only needed for RMII.

Please read the Advisory 1.0.16 in the AM335x Silicon Errata if you plan to use RMII.  Also read Advisory 1.0.18 if you plan to use RMII and Ethernet boot.

Regards,
Paul

Hello Peaves,

thank you for your quick reply, I do plan to use DP83848 in the MII mode and yes the only thing I need to know is the internal pull-up/pull-down state of the RX_DV and TXD_3 pins. How do I find out what is the state and what is the internal resistor value, because the Product review only gives me the presence or absence of PU/PD?

It is kinda weird that I wasn't able to find the value of the pull-up/pull-down resistor values for the DP83848. I did read both the advisory and I'm thinking that neither one should affect me since I'm using MII mode. The PHY has a default of MII mode, and I don't want to change it.

Can you please point me to where I can find the details about the internal resistor values? Also does the Linux distribution from TI include drivers for the national PHY?

Thank you for your patience and replies.

Regards

Santhosh

The effective pull-up/pull-down strength of internal resistors is provided in the Input leakage current electrical parameter of the respective IO.  Please look in the DC Electrical Characteristics section of the AM335x data sheet.

The default state of the internal pull-up/pull-down resistors can be found in the Ball Reset State and Ball Reset Rel. State columns of the Ball Characteristics table in the AM335x data sheet.  If these columns contain a value of 1(PU) or H, the terminal has the internal pull-up enabled.  If these columns contain a value of 0(PD) or L, the terminal has the internal pull-down enabled.  The Ball Reset State column represents the state while rest is applied and Ball Reset Rel. State column represents the state after reset has been released.

Regards,
Paul

Hello Paul,

I've completed the Ethernet PHY section of the design, would you mind taking a look at it. Could you please take a look at just the schematic for the PHY?

Thank you for all your replies.

Regards

Santhosh