Access S29NS Spansion NOR from x-loader in DM3730.

Progress update:

- I've enabled GPMG_TIMEOUT_CONTROL and checked the GPMC_ERR_TYPE register when the access to address 0x0000000 blocks, but it seems there's no error in the GPMC module.

- As GPMC is connected with the MPU through the L3 interconnect module I verified possible errors in this module and found out the following:

• LS_SI_FLAG_STATUS_0 reg is 0x0000_0004 which means there is a "Functional Inband Error" in the MPU.
• L3_IA_ERROR_LOG (MPU) reg is 0x8400_1a00  which means that the MPU has received an In-band error.
• L3_TA_ERROR_LOG (GPMC) reg is 0x0000_0000 which means that the GPMC module has not received an error.

Keepin the above in mind, it seems that the problem is not in the GPMC module itself.

Furthermore, when the I get control of the device with the JTAG I can access address 0x00000000 and read the NOR without problems.

Hi Javier,

I am an Application Engineer in Spansion. I see that you are using Spansion NOR device and having some issues.

Since you can access to the Flash using the JTAG connection, it seems all connections are set up correctly. Have you tried to configure the GPMC to use the Flash at a different base address? That may give you some hints into the problem.

Best regards,

Zhi Feng

Hi Zhi Feng,

I tried the following as base address but the problem is exactly the same: 0x08000000

Hi Javier,

Since the issue is unlikely related to the Flash, I may not be much helpful.

I did find a link which talks about the clock set up between the GPMC and the L3 module. You may want to take a look to see if it will help you.

http://processors.wiki.ti.com/index.php/Tips_for_configuring_OMAP35x_and_AM-DM37x_GPMC_registers

Best regards,

Zhi Feng

Hi Zhi Feng,

following your advice [1] and another document I could find [2] I've manage to get rid of the blocking problem.

However, I can only read "0"s from the NOR. I've configured the S29NS512P in Synchronous read mode as follows:

GPMC_REGISTERS
GPMC_CONFIG_1: 0xe3481201
GPMC_CONFIG_2: 0x00101500
GPMC_CONFIG_3: 0x00020280
GPMC_CONFIG_4: 0x10031506
GPMC_CONFIG_5: 0x02131115
GPMC_CONFIG_6: 0x8f030000
GPMC_CONFIG_7: 0x00000c48

Since my L3 freq is 165MHz I use GPMCFCLKDIVIDER=1 so that GPMC_CLK is 82,5MHz which sould be supported by this NOR flash.
The other configuration parameters have been configured according to [1] and p23 of [2].

[1] http://processors.wiki.ti.com/index.php/Tips_for_configuring_OMAP35x_and_AM-DM37x_GPMC_registers

[2] http://e2e.ti.com/cfs-filesystemfile.ashx/__key/CommunityServer-Discussions-Components-Files/537/1263.SpansionNOR_2D00_AM35x.pdf

Hi Javier,

Good to hear that you are making progress.

When you say you can only read "0" from Flash, do you mean that you get correct data from address 0, but not correct data from address 1, etc? Are these two reads from the same burst sequence or two different read cycles?

Were you using the debugger through JTAG when reading? Were you able to program to the device? How do you know data from "0" is correct?

Note that in order to do synchronous read from NS-P, you need to set up the configuration register properly. Please refer to Section 6.3.5 of the S29NS-P datasheet, which you can get from http://www.spansion.com/Products/Parallel-Flash/Pages/Spansion%20NS-VS-XS.aspx

You may try to read the value of configuration register before doing burst reads to make sure it is compatible to the GPMC settings.

Thanks,

Zhi

Applications Engineering
Spansion Inc.

HELLO 

          If the cs0 is connected to the NOR flash.so the base address is 0x0000 0000.

          So the

GPMC_CONFIG_1: 0xe3481201
GPMC_CONFIG_2: 0x00101500
GPMC_CONFIG_3: 0x00020280
GPMC_CONFIG_4: 0x10031506
GPMC_CONFIG_5: 0x02131115
GPMC_CONFIG_6: 0x8f030000
GPMC_CONFIG_7: 0x00000c48 should be 0x0000 0840

FOR THE REASON AS BELOW:

(((size & 0xF) << 8)        |        ((base >> 24) & 0x3F)       |        (1 << 6))

                |                                                    |                                           |

             SIZE                                     BASE ADDR                             CS

size should be 0x8( 128M ),and the base is 0x0000 0000,and the cs should be the enabled.

thanks

ps this is just not tested for I do not have a nor device by hand.thanks for reading and hope this will help u.

lu edward said:

HELLO 

          If the cs0 is connected to the NOR flash.so the base address is 0x0000 0000.

          So the

GPMC_CONFIG_1: 0xe3481201
GPMC_CONFIG_2: 0x00101500
GPMC_CONFIG_3: 0x00020280
GPMC_CONFIG_4: 0x10031506
GPMC_CONFIG_5: 0x02131115
GPMC_CONFIG_6: 0x8f030000
GPMC_CONFIG_7: 0x00000c48 should be 0x0000 0840

FOR THE REASON AS BELOW:

(((size & 0xF) << 8)        |        ((base >> 24) & 0x3F)       |        (1 << 6))

                |                                                    |                                           |

             SIZE                                     BASE ADDR                             CS

size should be 0x8( 128M ),and the base is 0x0000 0000,and the cs should be the enabled.

thanks

ps this is just not tested for I do not have a nor device by hand.thanks for reading and hope this will help u.

[[quote user="Zhi Feng"]

Hi Javier,

Good to hear that you are making progress.

When you say you can only read "0" from Flash, do you mean that you get correct data from address 0, but not correct data from address 1, etc? Are these two reads from the same burst sequence or two different read cycles?

[/quote]

I mean that I always read "0"s no matter what adress I am reading.

Zhi Feng said:

Were you using the debugger through JTAG when reading? Were you able to program to the device?

Yes, but I was using asynchronous mode. So I have known data stored in the first sector of the NOR. For performance reasons my goal is being able to read and write in synchronous burst mode.

Zhi Feng said:

Note that in order to do synchronous read from NS-P, you need to set up the configuration register properly. Please refer to Section 6.3.5 of the S29NS-P datasheet, which you can get from http://www.spansion.com/Products/Parallel-Flash/Pages/Spansion%20NS-VS-XS.aspx

You may try to read the value of configuration register before doing burst reads to make sure it is compatible to the GPMC settings.

Let me update my progress until now.

1. I configure the GPMC to use synchronous read with burst disabled:

#define LIMVA_NOR_GPMC_CONF1        0xc3081201
#define LIMVA_NOR_GPMC_CONF2        0x00101300
#define LIMVA_NOR_GPMC_CONF3        0x00020280
#define LIMVA_NOR_GPMC_CONF4        0x10031306
#define LIMVA_NOR_GPMC_CONF5        0x02111113
#define LIMVA_NOR_GPMC_CONF6        0x8F030000

#define LIMVA_NOR_GPMC_CONF7        0x00000c48

With burst disabled I can read the NOR data properly.

2. I set NOR configuration register so that it does 16word bursts instead of continuous burst.

The default value of the NOR configuration register was 0x6fc8 0xffef. I've changed it to 0x6fcb 0xffef to support 16word burst.

3. I configure the GPMC to enable burst mode:

#define LIMVA_NOR_GPMC_CONF1_BURST    0xe3081201
#define LIMVA_NOR_GPMC_CONF2        0x00101300
#define LIMVA_NOR_GPMC_CONF3        0x00020280
#define LIMVA_NOR_GPMC_CONF4        0x10031306
#define LIMVA_NOR_GPMC_CONF5        0x02111113
#define LIMVA_NOR_GPMC_CONF6        0x8F030000

#define LIMVA_NOR_GPMC_CONF7        0x00000c48

Now, with burst mode enabled I have the same problem that I stated before: I read all "0"s from every NOR address I try.

Do I have to modify also the number of wait states in the NOR configuration register?

Just another question:

I've read in [1] that there is no way to make the L3  issue transactions that are larger than 64 bits. This means that burst access will be always splitted into 4words. However, according to the datasheet, the S29NS512P does not support 4 words burst, the minimum is 8.

Will the NOR flash work in burst mode with the previous issue?

[1] http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/43106.aspx

Hi Javier,

If the Flash is set up to do 8-word burst but the host only does 4, it is fine. The host does not have to always complete the whole burst sequence.

As per your previous post, the config register value you set is 0x6FCB, 0xFFEF. That gives 13 wait state, which is the default. I am not sure that is correct in your system. You may want to try out a shorter wait state, ex. 8 clocks. The value for 8 clock wait state would be 0x47CB, 0xFFEF.

You may want to double check the GPMC settings to see how many clocks it waits before latching data.

It would be more clear to debug this issue with a logic analyzer on the bus. You can see exactly how the synchronous read works. Even if you just hook up a few pins with an oscilloscope, it will help.

Of course, modifying the CR to a different value is much simpler. You may want to try out a few shorter wait state to see if you recognize any of the data coming back.

Best regards,

Zhi Feng

Applications Engineering
Spansion Inc.

Hi Javier,

I haven't seen your posts for couple days. Have you been able to set up the burst mode? If so, could you reply with what mainly you did to make it work? We can all benefit from the information.

Best regards,

Zhi Feng

Applications Engineering
Spansion Inc.

Hi,

sorry for the delay. It was a problem with the configuration of the WAIT pin in my SoC. Now it works fine.

Regards.