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MIPI-DSI Graphics Data Seems Missing

Other Parts Discussed in Thread: OMAP3530

I want to use my MIPI-DSI connected video mode LCD panel outside of Linux.  Under Linux I was able to get the MIPI-DSI video mode panel to work and it looks great.  So I did a snapshot of the DISPC and DSI registers under Linux while the LCD panel was working properly so I could try to replicate that configuration.

I have written code that configures the DSI and DISPC (and basic clock/DSS stuff), and have tried to follow Section 15.6.7 in the OMAP3530 TRM (rev. T) to do so (although I need to use GFX instead of the VID case that 15.6.7 uses).  This code includes appropriate waiting for bits to clear and making sure not to modify bits when enables don't allow it.  After significant strugglings, I have the PLL working, the DSI port outputting what looks like basically good data, including being able to read back the correct ID from the LCD panel.  Further, with the DISPC and VC0 enabled, I get what looks like good framing information and timing.  It appears identical to the Linux case, including the low speed transitions for vertical frame syncs and the high speed packets of horizontal framing info.

In spite of getting all this working, however, there is nothing on the screen and moreover, the MIPI high speed pixel data looks to be all zeros (between the horizontal framing packets).  In other words, although the timing and framing seems to be good, only black pixels are output.

I have tried changing the graphics default colors, the frame buffer to all 0xff's, but to no avail.  All the pixels coming out of the DSI block stay black.  Is there something in the connection between the DISPC and DSI that I might be missing, such that the DSI wouldn't actually receive DISPC data?

Attached is the registers dumped from DISPC and DSI: 2350.regs.txt

Thanks much for any suggestions,

Chris

  • Changed my code to follow the register modificaiton sequence in section 15.5.4.8:

    • DSS.DSI_VCn_CTRL[0] VC_EN bit set to 1
    • DSS.DSI_VCn_CTRL[4] MODE bit set to 1
    • DSS.DSI_VCn_LONG_PACKET_HEADER register access
    • DSS.DSI_VCn_CTRL[0] VC_EN bit set to 1

    Where it was writing to the long packet header register for Table 15-109 and it started to work!