How do you control the AM335x EMIF ODT for DDR2/3 reads?

rperezti

All,

I see how to control the ODT for the DDR2/3 memory device which applies during writes, but how do I control the ODT on the AM335x which applies during reads.

A similar question was asked and answered for the AM35xx EMIF. Does the answer for AM35xx found at this post also apply to AM335x? https://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/int_sitara_am35x/f/422/t/114550.aspx

Ruben

over 13 years ago

0 JJD over 13 years ago

TI__Guru* 86880 points

Ruben, it is similar to AM35x but the register is in a different location. This is controlled in the DDR_PHY_CTRL_1 register. Currently the Rev C of the TRM is missing this information. Below is the updated information which will make it into a new revision of TRM which should be coming in the next couple of weeks.

0 rperezti over 13 years ago in reply to JJD

TI__Genius 12670 points

JJD said:

Ruben, it is similar to AM35x but the register is in a different location. This is controlled in the DDR_PHY_CTRL_1 register. Currently the Rev C of the TRM is missing this information. Below is the updated information which will make it into a new revision of TRM which should be coming in the next couple of weeks.

JJD, thanks for the response. The attachement doesn't show up. Can you please try attaching it again. Thanks

0 JJD over 13 years ago in reply to rperezti

TI__Guru* 86880 points

Retry

0 JJD over 13 years ago in reply to JJD

TI__Guru* 86880 points

0825.DDR_PHY_REG.doc

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How do you control the AM335x EMIF ODT for DDR2/3 reads?