ezdsp_demo program hangs when PLL is initialized?

MikeH

When attempting to run the ezdsp_demo program in SDRAM on my ezdsp5502 board, the program freezes during a call to the CSL PLL_setFreq. Can anyone give some insight into what may be going on?

void initPLL(void)
{
    PLL_config(&myCfg); 
    
    /*Parameters for PLL_setFreq are:   
    enable/mode, multiply, divider0, divider1, divider2, divider3, osc divider
    
        mode  = 1 means PLL enabled (non-bypass mode)
        mul   = 15 means multiply by 15
        div0  = 0 means divide by 1 using PLLDIV0
        div1  = 3 means divide by 4 using PLLDIV1
        div2  = 3 means divide by 4 using PLLDIV2
        div3  = 3 means divide by 4 using PLLDIV3
        oscdiv= 1 means divide by 2 using OSCDIV1
    */
    
    /* Set the required frequency for CPU, Fast and Slow peripherals and EMIF */
    PLL_setFreq(1,15,0,3,3,3,1); // CPU @ 300 MHz, others @ 75MHz
    
}

over 13 years ago

0 MikeH over 13 years ago

Guru 15580 points

From SPRA924A...

The PLLDIV3 register should not be set in a manner that makes the frequency for the EMIF
Clock Group greater than 100 MHz or greater than the frequency of the Fast Peripherals Clock
Group, whichever is smaller. There must be no external memory accesses when the value of
PLLDIV3 is being changed, this means that the frequency of the EMIF Clock Group cannot be
changed by a program that is being executed from external memory. It is recommended that the
EMIF be put in IDLE mode before changing the PLLDIV3 value.

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ezdsp_demo program hangs when PLL is initialized?