Configuring McASP for the AM3358 using Starterware (Beaglebone)

hi Tom,

Beagle Bone doesnt have direct audio ports, Hence, we have not provided examples.

Please check the release notes @  http://processors.wiki.ti.com/index.php/StarterWare_02.00.00.06_Release_Notes for the examples supported for beaglebone / evmAM335x.

Also, there is no definition for McASPPinMuxSetup()  for beaglebone.

Cheers,

Sujith.

Hi

Thanks for your prompt reply.

I would like to build my own audio daughter board (cape) for the Beaglebone. Is there really no way to get this project going with Starterware as is (I would be terribly suprised)?

Thanks

Tom

Hi Suijith,

I'm sorry for reopening this thread but I'm almost done porting the EVM-McASP project to the BeagleBone and I just need to figure out how to modify the McASPPinMuxSetup() code. Can you please tell me how to change the code to work with McASP0:

 HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = 
 CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE 
 | MCASP_SEL_MODE; 
 HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) = 
 CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
 | MCASP_SEL_MODE; 
 HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
 CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
 | MCASP_SEL_MODE; 
 HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) = 
 CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE 
 | MCASP_SEL_MODE; 
 status = TRUE;

Thanks

Hi Tom,

The pin multiplex will be entirely different for McASP0. For pin mux details, please refer to the section 7.13 of Beagle Bone SRM . You can refer to the pin mux functions for any peripheral to see how this is to be done.

Also, please find the details on BeagleBone here 

Cheers,

Sujith.

Hi Sujith,

I am trying to use McASP0 with AIC3106 codec on BeagleBone A3. I am using the AM335X_StarterWare_02_00_00_06.

My problem is when I execute the mcaspPlayBk example, it will blocking at 

while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

XDATA bit can not cleared to zero ...

Could you please tell me where the problem is ?

Note: I am using I2C1 connect to codec.

1. In include/hw/soc_AM335x.h I have defined that I am using McASP0 as given below.

#define SOC_MCASP_0_CTRL_REGS                (0x48038000)
#define SOC_MCASP_0_FIFO_REGS                (SOC_MCASP_0_CTRL_REGS + 0x1000)
#define SOC_MCASP_0_DATA_REGS                (0x46000000)

2. In platform/beaglebone/mcasp.c add McASP0 pin mux and clock configuration.

  #include "beaglebone.h"

unsigned int McASP0PinMuxSetup(void)
{
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(8)) = 
                  CONTROL_CONF_RXACTIVE 
                  | CONTROL_CONF_MUXMODE(3); // mcasp0.aclkx            
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(9)) = 
                  CONTROL_CONF_RXACTIVE
                  | CONTROL_CONF_MUXMODE(3); // mcasp0.fsx            
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(12)) =
                  CONTROL_CONF_RXACTIVE
                  | CONTROL_CONF_MUXMODE(4); // mcasp0.axr2            
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(13)) = 
                  CONTROL_CONF_RXACTIVE 
                  | CONTROL_CONF_MUXMODE(4); // mcasp0.axr3            
    
    return TRUE;
}

void McASP0ModuleClkConfig(void)
{
    HWREG(SOC_PRCM_REGS + CM_PER_MCASP0_CLKCTRL) =
                             CM_PER_MCASP0_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_PRCM_REGS + CM_PER_MCASP0_CLKCTRL) &
      CM_PER_MCASP0_CLKCTRL_MODULEMODE) != CM_PER_MCASP0_CLKCTRL_MODULEMODE_ENABLE);


    /*
    ** Waiting for IDLEST field in CM_PER_MCASP0_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_MCASP0_CLKCTRL_IDLEST_FUNC <<
           CM_PER_MCASP0_CLKCTRL_IDLEST_SHIFT)!=
          (HWREG(SOC_CM_PER_REGS + CM_PER_MCASP0_CLKCTRL) &
           CM_PER_MCASP0_CLKCTRL_IDLEST));
}

3. In example/beaglebone/mcasp/mcaspPlayBk.c I have changed SOC_MCASP_1_DATA_REGS to SOC_MCASP_0_DATA_REGS

  #include "beaglebone.h"

static struct EDMA3CCPaRAMEntry const txDefaultPar = 
       {
           (unsigned int)(OPT_FIFO_WIDTH), /* Opt field */
           (unsigned int)loopBuf, /* source address */
           (unsigned short)(BYTES_PER_SAMPLE), /* aCnt */
           (unsigned short)(NUM_SAMPLES_LOOP_BUF), /* bCnt */ 
           (unsigned int) SOC_MCASP_0_DATA_REGS, /* dest address */
           (short) (BYTES_PER_SAMPLE), /* source bIdx */
           (short)(0), /* dest bIdx */
           (unsigned short)(PAR_TX_START * SIZE_PARAMSET), /* link address */
           (unsigned short)(0), /* bCnt reload value */
           (short)(0), /* source cIdx */
           (short)(0), /* dest cIdx */
           (unsigned short)1 /* cCnt */
       };

static struct EDMA3CCPaRAMEntry const rxDefaultPar =
       {
           (unsigned int)(OPT_FIFO_WIDTH), /* Opt field */
           (unsigned int)SOC_MCASP_0_DATA_REGS, /* source address */
           (unsigned short)(BYTES_PER_SAMPLE), /* aCnt */
           (unsigned short)(1), /* bCnt */
           (unsigned int)rxBuf0, /* dest address */
           (short) (0), /* source bIdx */
           (short)(BYTES_PER_SAMPLE), /* dest bIdx */
           (unsigned short)(PAR_RX_START * SIZE_PARAMSET), /* link address */
           (unsigned short)(0), /* bCnt reload value */
           (short)(0), /* source cIdx */
           (short)(0), /* dest cIdx */
           (unsigned short)1 /* cCnt */
       };

static void McASPI2SConfigure(void)
{
    McASPRxReset(SOC_MCASP_0_CTRL_REGS);
    McASPTxReset(SOC_MCASP_0_CTRL_REGS);

    /* Enable the FIFOs for DMA transfer */
    McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
    McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

    /* Set I2S format in the transmitter/receiver format units */
    McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
                     MCASP_RX_MODE_DMA);
    McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
                     MCASP_TX_MODE_DMA);

    /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
    McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 
                        MCASP_RX_FS_EXT_BEGIN_ON_RIS_EDGE);
    McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 
                        MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);

    /* configure the clock for receiver */
    McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
    McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 
    McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
                          0x00, 0xFF);

    /* configure the clock for transmitter */
    McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
    McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 
    McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
                          0x00, 0xFF);

    /* Enable synchronization of RX and TX sections  */  
    McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

    /* Enable the transmitter/receiver slots. I2S uses 2 slots */
    McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
    McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

    /*
    ** Set the serializers, Currently only one serializer is set as
    ** transmitter and one serializer as receiver.
    */
    McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
    McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

    /*
    ** Configure the McASP pins 
    ** Input - Frame Sync, Clock and Serializer Rx
    ** Output - Serializer Tx is connected to the input of the codec 
    */
    McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
    McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AXR(MCASP_XSER_TX));
    McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX 
                                               | MCASP_PIN_ACLKX
                                               | MCASP_PIN_AFSR
                                               | MCASP_PIN_ACLKR
                                               | MCASP_PIN_AXR(MCASP_XSER_RX));
}

static void I2SDataTxRxActivate(void)
{
    /* Start the clocks */
    McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
    McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);

    /* Enable EDMA for the transfer */
    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP1_RX,
                        EDMA3_TRIG_MODE_EVENT);
    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP1_TX,
                        EDMA3_TRIG_MODE_EVENT);

    /* Activate the  serializers */
    McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
    McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

    /* make sure that the XDATA bit is cleared to zero */
    while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

    /* Activate the state machines */
    McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
    McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

Hi Ricky,

You are still referencing McASP1, i.e.:

    /* Enable EDMA for the transfer */
    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP1_RX,
                        EDMA3_TRIG_MODE_EVENT);
    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP1_TX,
                        EDMA3_TRIG_MODE_EVENT);

Don't know if this is correct though!

Looking forward to get this project working.

Thanks

Tom

Hi Thomas,

Thanks for your reply.

You are right, I miss the EDMA events, I have added two events for McASP0 in include/armv7a/am335x/edma_event.h

  #define EDMA3_CHA_MCASP0_TX               (8u)

  #define EDMA3_CHA_MCASP0_RX               (9u)

Now XDATA bit will be clear to zero.

Thanks.