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MSMC Shared region

ankit jain
Prodigy 200 points

Hi,

I am working on C6670 hardware platform and facing cache coherency issues. I know by default MSMC is cacheable but i want to make part of MSMC to be non-cacheable.For this i created a shared region in MSMC, and set its properties to be non-cacheable. This is how i created a shared memory region in my .cfg files for core0,core1 and core2 .

SharedRegion.setEntryMeta(0,
    { base: 0x0C010000,
      len: 0x00070000,
      ownerProcId: 0,
      isValid: true,
      cacheEnable:false
      name: "sharemem",
    });

But while allocating memory from this shared region using "Memory_alloc ((xdc_runtime_IHeap_Handle)  SharedRegion_getHeap(0), num_bytes, 0, &errorBlock)"; cache seems to be enabled in this region.

Can you please let me know why cache is getting enabled in this region, even though i am explicitly setting cacheEnable : False.

Thanks,

Ankit

  • 0
    Mastermind 6670 points

    Hi,

    The MCSM accessed from address 0x0C000000 cannot be make uncachable: it is always cachable in L1 and non-cachable in L2.

    You have to remap the memory at an external memory address. Note also that cacheability is configurable with a granularity of 16M bytes (see sprugw0, para. 4.4.4).

    I don't know how you can manage this with the SYS/BIOS  configuration.

  • 0 in reply to Alberto Chessa
    Prodigy 200 points

    Is there any sample example code which i can refer to for making this part non-cacheable ?

    Thanks,

    Ankit

  • 0 in reply to ankit jain
    Intellectual 830 points

    Hi Ankit, I don't know of sample code, but here are some things you must look at:

    SPRUGW0B Table 4-20 shows that MSMC (0x0C000000-0x0C3FFFFF) is covered by MAR12, which is shaded in the table and thus its cachability can't be changed.

    You must pick an unused section of memory space, and map a portion of MSMC to that address at run-time using XMC/MPAX, see SPRUGW0B Section 7.3.

    You must modify your memory layout: When using BIOS/XDC, do this in CCS:

    Tools -> RTSC Tools ->Platform -> Edit/View, then select your package and edit the memory map. See SPRUEX3K (SYS/BIOS RTOS user guide) section 6.2.

    You may have to modify your linker directives to place data in the non-cachable region, See SPRU186V (Assembly tools), Chapters 2 and 7 (linker), although maybe your .cfg file can do that for you.

    The TI docs on the web may hint at all this. I think the tutorial about the MAD utils talked about some of the above.

    Regards, Jonathan