OMAP4430 MEMORY MAP OVERVIEW

Hi,

The Level 1 (L1) memory is cache memory local to each module, it is not shared between them.

You can see that in the 4430 TRM:

1.3.1 Cortex-A9 MPU Subsystem Description
The Cortex-A9 MPU subsystem integrates the following submodules:
• ARM Cortex-A9 MPCore
– Two ARM Cortex-A9 central processing units (CPUs)
– ARM Version 7 ISATM: Standard ARM instruction set plus Thumb®-2, Jazelle® RCT and Jazelle
DBX JavaTM accelerators
– NeonTM SIMD coprocessor and VFPv3 per CPU
– Interrupt controller (Cortex-A9 MPU INTC) with up to 128 interrupt requests
– One general-purpose timer and one watchdog timer per CPU
– Debug and trace features
– 32-KB instruction and 32-KB data level 1 (L1) caches per CPU
• Shared 1-MB level 2 (L2) cache
• 48 KB bootable ROM
• Local power, reset, and clock managment (PRCM) module
• Emulation features
• Digital phase-locked loop (DPLL)

1.3.3 Cortex-M3 MPU Subsystem Description
The Cortex-M3 MPU subsystem includes the following components:
• Two Cortex-M3 CPUs: One for SIMCOP control, and the other for RTOS, ISP, and display subsystem
control
• ARMv7-M and Thumb-2 instruction set architecture
• Dedicated INTC with up to 64 physical interrupt events
• Two-level memory subsystem hierarchy
– L1
• 32-KB shared cache memory
– L2 ROM + RAM
• 64-KB RAM
• 16-KB bootable ROM
• Cortex-M3 system bus directly connected to the ISS interconnect
• MMU for address translation
• Integrated power management
• Emulation feature embedded in the Cortex-M3

For communication between A9, M3 and DSP there is the L3 interconector

Thanks Israel Cepeda for your reply.

I got clear with your answer partially.

As mentioned in TRM  2.2 that is-

The system memory mapping is flexible, with two levels of granularity for target address space allocation:
• L1: Four quarters are labeled Q0, Q1, Q2, and Q3. Each quarter corresponds to a 1-GB address space
(total address space is 4GB)..

L2: Each quarter is devided into 8 blocks of 32 MB each

I come to know that L1(not cache memory) having four quarters that is  Q0(1GB) is the BOOT SPACE/GPMC ,Q2 AND Q3 is DDR address space .

But my doubt is that whether the Q1 mentioned here is the part of  all three subsystems Cortex-A9 MPU, Cortex™-M3 MPU, and DSP subsystems or it is local to each module ?

-Studinstru

Its accessible by all three subsystems A9,M3 and DSP. Its not local to any single module.

Studinstru,

Ok, so you are only talking about the L3 Memory Space Mapping..

That is 4GB as you mentioned, if you want to see the details how it is divided you can see: Table 2-1. Global Memory Space Mapping

I don't now if one of the reserved are the memory for the subsystems you mentioned, but looking in the Interconnect part I found:

13.1.2 Architecture Overview
The device memory hierarchy includes four levels:
• Level 1 (L1) is internal to the central processing units (CPUs). It concerns data exchange with the internal Level1 cache memory subsystem,
and it is the closest memory to the microprocessor unit (MPU) core and the IVAHD core.
• Level 2 (L2) is included in the IVAHD subsystem and the MPU subsystem.
• The chip-level interconnect consists of one level 3 (L3) interconnect and four level 4 (L4) interconnects. It enables communication among the modules and subsystems in the device.
Figure 13-1 shows an overview of the L3 and L4 interconnect architecture.

So for those modules seems to be local, and can be access using L3.

So going to the original question, I think there is no direct access between L1 on those subsystems like in ABE and MPU subsystem, you have to use L3. For ABE it has memory mapped also to MPU in order to make things faster:

Audio back-end (ABE) 0x4010 0000 0x401F FFFF 1MB ABE domain (direct Cortex-A9 MPU access).

Hope this helps

Thanks to Ranjith and Israel.

As per our discussion on this forum, I come to the following conclusion :

-----------------------------------------------------------------------------------------------------------------------

1) The coretx A9 having :

L1 I Cache: 32 KB / CPU

L1 D cache:32 KB / CPU

L2  Shared by two cortex : 1MB

2)Available On chip memory (4GB):

- Q0 :1GB >>GPMC

- Q1 : 1GB >>  Boot ROM : 48KB , SAR ROM :4KB,SAR RAM : 8KB, L3 OCM_RAM : 56KB etc..

- Q2 :1GB >> SDRAM

- Q3 :1GB >> SDRAM

-------------------------------------------------------------------------------------------------------------------------------

Please give your comments ..........

-Studinstru.

Thanks Israel.

I understood this point and I was trying to access LPDDR2 memory location starting from 0X8000 0000 with length of  1GB .

I mentioned this origin and length of LPDDR2 memory  in linker cmd  file , but i am getting "A data verification error occurred ,file load failed "

Means that LPDDR2 memory i am not able to access .......

How should I access this memory  for my use (1GB)........

-Studinstru

Hi Magdalena,

I will go with the new thread .

Please reply...

-Studinstru