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AM3894 fast DDR2 access problem : read and write in same time, it going to broken

Min Chul KIM
Prodigy 140 points
Other Parts Discussed in Thread: AM3894

4834.aaa.zipDeer TI, thank you for read.
This is a question for AM3894 DDR2 write and read problem when it happen in almost same time.
We hope someone has answer or helpful information to solve this critical issue. It is emergency for us.

First, we have designed system to capturing 14bit( = 16bit with padding 2bits) WORD pixels from special sensor that it connected with LVDS cable.
Spartan3(FPGA) has programmed capturing sensor signal into FIFO and it stores in internal buffer by toggling EDMA transfer.
When it start to capture, FIFO and AM3894 EDMA directly stores image data into DDR2 memory (0xC0000000 ~ ) and while doing store, embedded linux application reads stored data thru cmem driver for send data via TCP/IP socket.

Second, problem occurs when it works on GbE connection, about 1 to 2 seconds passed reading data crashes. Actually written data was crashed.
We suppose to it crash when write and read in same time.
When it connected as 100Mbps TX, crashing data is less occurs than GbE.
And absolutely, finishing write without read action then read them, there’s no problem.


Here is our block diagram.

 


We uses PSP 4.0.0.12 and customized own DMA driver based your source.
Cmem also used last version of yours , and adjusted virtual memory size.

So, we want to know how it be solved by using what kind of solution like interleaving for DDR2 write & read.
We attaches our memory setting source code in uboot. (plz refer to aaa.zip file)

Regards, Raphael Kim.

  • 0
    TI__Guru* 84110 points

    Raphael Kim,

    What do you mean by "crash"?

    Writing to one area of DDR2 while reading from another area of DDR2 is okay and will not cause problems. If two masters try to access DDR2 at the same time, both will execute at different times if they are going to the same EMIF or at the same time if they are going to different EMIFs.

    Please look through the errata document to see if there are any access situations that may cause problems for your specific situation. But I do not know of anything that would cause the problem you have described.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 140 points

    Dear RandyP.
    That "CRASH" meant "Conflict" in same address accessing as you written.
    And we have to do best for solving this problem.

    Thank you very much, RandyP.
     

  • 0 in reply to Min Chul KIM
    TI__Guru* 84110 points

    If I understand correctly, you are writing to a buffer and at the same time you are reading from that same buffer. Is this correct?

    It appears that you are reading from the buffer too fast, so that you are reading from locations in the buffer that have not yet been written to. This race condition will always be a problem. It is usually solved by using two buffers, commonly referred to as a ping-pong buffering method.

    Is this your problem, and could this be your solution?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 140 points

    Dear RandyP.

    Yes, but there's something special argument, maybe it is a condition.
    We have a driver to access DDR2 memory from FIFO(FPGA) memory for copying 16bit data array with eDMA.
    and embedded linux application approaching written memory address with cmem drivers (referenced address to  physical memory address).
    Actually it maybe not really same time access in once, but it will be really seems like same time - write and read in just between really close clock ?

    I think it need to be changed to DDR3 for enough read and write bandwidth.
    But  face up to reality, PCB artwork done, and we don't have to change components and circuits.
    Want to find the way, just all.

    Thanks :) 

  • 0 in reply to Min Chul KIM
    TI__Guru* 84110 points

    Could this also be a cache coherency problem?

    The EDMA will copy from the FIFO(FPGA) to the DDR2 memory. If the Cortex-A8 reads from that buffer in DDR2, it will store some of that data in its cache memory. The next time the EDMA copies new data from the FIFO(FPGA) to the DDR2, the Cortex-A8 may still have some portions stored in cache memory and would not read the correct new data from DDR2.

    If the buffer is smaller than the A8's cache, this could be an issue. If the buffer is significantly larger than the A8's cache, and if the linux application reads the entire buffer sequentially, then this would probably not be the problem.

    Regards,
    RandyP