Hi Dear,
We are working on DM8168 EVM (Netra) based custom board.
Custom setup is as said below:
We have DM8168 processor video ports connected to FPGA logic, where FPGA will take 1080i-60 embedded sync data (BT.1120) from DM8168 for transmitting and gives 1080i-60 embedded sync data (BT.1120) to DM8168 while receiving with 16-bit lines.
Following are the settings done while execution:
1) Ti81xxvin.ko is built with removing all the sub-device part removed as we are not using any decoder (TVP).
Modified source codes is attached: ti81xx_fb.c & ti81xxvin_main.c (all modifications tagged with /* SADA */ )
2) Ti81xxhdmi.ko is not installed as we are not using on-chip HDMI.
3) Custom board booted with following boot arg.
“notifyk.vpssm3_sva=0xBF900000”
4) Following “load-hd-firmware.sh” used for loading the Video modules
#!/bin/sh
#
# manage HDVICP2 and HDVPSS Engine firmware
PATH=$PATH:/usr/share/ti/ti-media-controller-utils
HDVICP2_ID=1
HDVPSS_ID=2
case "$1" in
start)
echo "Loading HDVICP2 Firmware"
prcm_config_app s
modprobe syslink
until [[ -e /dev/syslinkipc_ProcMgr && -e /dev/syslinkipc_ClientNotifyMgr ]]
do
sleep 0.5
done
firmware_loader $HDVICP2_ID /usr/share/ti/ti-media-controller-utils/dm816x_hdvicp.xem3 start
echo "Loading HDVPSS Firmware"
firmware_loader $HDVPSS_ID /usr/share/ti/ti-media-controller-utils/dm816x_hdvpss.xem3 start
modprobe vpss sbufaddr=0xBFB00000 mode=hdmi:1080i-60,dvo2:1080i-60,hdcomp:1080i-60 i2c_mode=1
modprobe ti81xxfb vram=0:24M,1:16M,2:6M
fbset -depth 32 -rgba 8/16,8/8,8/0,0/0
modprobe ti81xxvo
modprobe ti81xxvin
;;
stop)
echo "Unloading HDVICP2 Firmware"
firmware_loader $HDVICP2_ID /usr/share/ti/ti-media-controller-utils/dm816x_hdvicp.xem3 stop
echo "Unloading HDVPSS Firmware"
rmmod ti81xxvin
rmmod ti81xxvo
rmmod ti81xxfb
rmmod vpss
firmware_loader $HDVPSS_ID /usr/share/ti/ti-media-controller-utils/dm816x_hdvpss.xem3 stop
rmmod syslink
;;
*)
echo "Usage: /etc/init.d/load-hd-firmware.sh {start|stop}"
exit 1
;;
esac
exit 0
5) Following sysfs settings are done for displaying (on vout0 port).
echo 0 > /sys/devices/platform/vpss/display1/enabled
echo 1080i-60 > /sys/devices/platform/vpss/display1/mode
echo double,yuv422spuv > /sys/devices/platform/vpss/display1/output
echo 1 > /sys/devices/platform/vpss/display1/enabled
Directing display to DVO2:
echo 0 > /sys/devices/platform/vpss/graphics0/enabled
echo 1:dvo2 > /sys/devices/platform/vpss/graphics0/nodes
echo 1 > /sys/devices/platform/vpss/graphics0/enabled
6) Following omx utility is used for capturing, built with 1080i-60 support modifications.
./capture_encode_a8host_debug.xv5T –o capture1.h264 –m 1080i –f 60 –b 1000000 –d 0 –n 50
Below are the Queries/issues that we are facing in this setup:
1) Display video output to FPGA logic:
For embedded Sync transmission:
A synchronization packet occurs immediately before the first active sample on every line, and immediately after the last active sample (and before the start of the horizontal blanking region). The synchronization packet consists of four 10-bit words. The first three words are always the same--0x3FF, 0, 0; the fourth consists of 3 flag bits, along with an error correcting code. As a result, there are 8 different synchronization packets possible.
Issue:
Sometimes we are getting FFFF, AC8F, 0000, and flag instead of FFFF, 0000, 0000 and flag. (Data seen at FPGA signal tapping)
Is there any configuration problem that missing for BT.1120, 1080i-60 embedded sync transmission? Please let me know. I didn’t change any source codes for video output path.
2) Capture video input from FPGA logic:
When I use above said omx utility following are the issues:
1. I am not able to capture more the 100 frames.
2. Capture video is not proper.
File is attached for your reference: capture1.h264
Please answer/suggest for my queries ASAP, this is a major blocker for our development.
Thanks in advance
Regards
Sadasivappa
