I have to use the EMIFA bus in asynchronous mode to interface an FPGA (through an Avalon master bridge). I need the maximum speed as possible for this interface and I have to manage the EMA_WAIT signal because, in some case, data are not ready immediately.
The timing requirements for EMIFA (sprs586c - OMAP L138 Datasheet.pdf, page 121-125) is not clear for me concerning the signal EMA_WAIT. I don't understand the meaning of the tsu (EMWEL-EMWAIT) timing which is 4 cycles (timing No 28 and 14). This means you must assert EMA_WAIT 4 cycles before the end of the strobe, implying that the write strobe (without wait) must be greater than 4 cycles in case you may have to assert the EMA_WAIT signal, or this means 4 cycles is minimum wait time if EMA_WAIT is asserted ? In the first case this imply you can't make fast transfer (with strobe of 1 or 2 cycles)... I'm disppointed...!
Another point is tw(EM_WAIT) which is 2 cycles (timing No 2). what's happended if the EMA_WAIT assertion is shorter? the wait may not be taken into account or the EMIFA may hang?
So the main question is how to do fast transfer (so having short strobe) but with the EMA_WAIT management ?
Thank you for your help