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TMS320C6657/4 data sheets questions

Other Parts Discussed in Thread: TMS320C6654

1. In table 7-2 on page 110 of the data sheet for TMS320C6654 it states in the row for "time stamp 6" that, "the maximum clock period is 33.33 nsec”...

a)  Is this the maximum clock period during configuration? What are the clocking frequency requirements during configuration?

b) Is there a document that explains/outlines/provides this information?

 

2. In table 7-2 on page 110 of the data sheet for TMS320C6654 it states in the row for "time stamp 3" that, "All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.”

a) Does this mean that all inputs have to be in a high impedance state? Or, can all inputs be set to the “low input state?”

  • Hector,

    1a) It's not time stamp, it's the time marked 6 in the power sequencing timing diagram above it.  That's the max period (translates to minimum frequency) that's supported.  This is specified to be 40MHz (25ns) and the description you for time 6 in the power sequencing needs to be fixed in in the data manual.

    1b) Not sure what needs to be explained, it's simply stating that the maximum period is 33.33ns (should be 25ns), it requires 500 SYSCLK1 cycles for stabilization, that translates to 16.6us, this should be 12.5us max for it to be stable.  I'm not sure where the confusion is.  If they used a higher speed clock then then it's still 500 SYSCLK1 cycles and the period would be smaller and the time would be smaller.

    2a) I'll have to confirm but I believe it would be fine for them to be pulled low.  Let me get back to you on this.

  • On 2a) I have followed up and driving this low is as valid as High-Z / Tristating the pins for this.

    Best Regards,
    Chad