AM387x GPMC_CLK(FCLK?)

Michi,

It is a bug in our doc and it is in progress to fix it.  The GPMC_FCLK is half speed of L3 interconnect so it is 100 MHz.

BR,

Viet

Viet-san,

Thank you for your reply.

I understood that current document has a bug. And GPMC_FCLK is half speed of L3 interconnect.

It is 100MHz maximum. And this condition is applied under opp166.

The sentence of the document must be modified as the above, must not it?

(1) Sync mode = 62.5MHz, Async mode=125MHz "  --->  (1) Sync mode = 50MHz, Async mode=100MHz

50MHz/100MHz frequency represents GPMC_FCLK.

Is my understanding right?

I appreciate your quick reply.

Best regards,

Michi

Michi,

Yes, you are corrected.

BR,

Viet

Dear Viet-san,

I hope you find this new post.

I have more questions.

I asked you about the sentence "Sync mode = 62.5 MHz; Async mode = 125 MHz".

And you adviced me correct is "Sync mode=50MHz, Async mode=100MHz." , and 50MHz and 100MHz represent GPMC_FCLK, not GPMC_CLK.

According to TRM, it is written that GPMC_CLK is kept low when access is defined as asynchoronous.

Why async mode =100MHz is defined as the above? And why sync mode is the half frequency of async mode?

Please let me know.

Best regards,

Michi

Viet-san,

Thank you for your quick reply.

I think the sentence "Sync mode=50MHz, Async mode=100MHz."  is wrong.

Please let me know the right sentence or the meaning of this sentence.

is this just represented GPMC_FCLK maximum frequency is 100MHz in Sync mode?

I really appreciate your support.

Best regards,

Michi

Yamamoto-san,

Working on my side on a DM814x project too.

As the L3/L4 core is specified to a maximum freq of 220MHz in the SPRS647C (in OPP166 mode), please confim that one can use 110MHz as the gpmc_fclk (i.e. sysclk6), resulting in a maximum 55MHz GPMC_CLK output freq for synchronous access ?

Also please confirm that for asynchronous AND synchronous access, all timings can be set externally based on the GPMCFCLKDIVIDER value, meaning that for a synchronous access, the output clock GPMC_CLK can not be higher than 27.5MHz if GPMCFCLKDIVIDER divides GPMC_FCLK by 2.

Last point : is there a more recent SPRS647 document, including maxumum CLOCK frequencies for OPP higher than 100 ?

Regards,

Jean-Michel,

I got from GPMC designer as the gpmc_fclk is synthesize at 100 MHz and guarantee up to 100MHz.

BR,

Viet

Thanks Viet,

If I'm correct, the GPMC_FCLK is directly derived from the L3 interconnect slow clock domain, and as this clock can be as high as 120MHz for OPP166 (L3/L4 maxi clock at 240MHz in some TI documentation, and same information found in the Linux Kernel source code with 240MHz settings option for L3/L4 PLL).

So if L3/L4 maximum freq is 240MHz for OPP166 on a CYE1 device at 1.35V, it means that GPMC_FCLK can be as high as 120MHz (60MHz for synchronous devices) under the same conditions.

Please correct wrong informations above to clarify this point.

Thanks in advance for your reply.

Jean-Michel,

You are corrected.  It is directly derived from L3 clock so the GPMC_FCLK can be as high as 120MHz in this case.  But, as I said earlier, gpmc_fclk is synthesized in design at 100 MHz and guarantee up to 100MHz. 

BR,

Viet

Thanks.

Page 1532, figure 11-48 of TRM rev A, CLK is drawn at the same speed as FCLK.

This is a synchronous access, and F is 104MHz from table 11-47.

Q1 : F can not be higher than 100MHz. Right ?

Q2 : For synchronous access, CLK output can not be higher than 50MHz. So the drawing is wrong, and GPMCFCLKDIVIDER must be set to /2 minimum. Right ?

Dear all at TI,

In the last TRM rev (SPRUGZ8C), this is now page 1718, figure 11-48.

This describes the SYNCHRONOUS burst read access.

The GPMC_FCLK is written to be at 100MHz in the table 11-47.

As synchronous mode for GPMC is limite to 50MHz (P <= 20ns), please confirm that this figure is not correct, and that it should represente CLK at half the frequency of FCLK, with GPMCFCLKDIVIDER also set to 2 minimum  ?  

Regards,

Hi Jean-Michel,

The TRM is corrected.  Please see this post for more detail on GPMC clk discussion:  http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/183641/662574.aspx#662574.

BR,

Viet