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DM816X DDR3 Differential Impedance Requirement

Kevin Cook
Prodigy 20 points
Other Parts Discussed in Thread: AM3894

We are implementing a DDR3 system for a DM816X that uses more routing layers than only TOP and BOTTOM. We have decided on a system Zo of 60 ohms which we control (not counting manufacturing tolerances) to within 2 ohms on all layers, which is permitted according to Table 8-18 No. 13. The PCI-e and SATA sub-systems require 60 ohm SE / 100 ohm differential, and the EVK seems to use something similar for all the DDR3 clocks and strobes, so it would seem logical to use the same.  In practice, 100 ohms differential is somewhat difficult to maintain in all the layers, so it would be helpful to know concrete MIN TYP and MAX values for the differential impedance (keeping in mind that we will always maintain 60 ohm SE). I do not see this information specified anywhere in the datasheet or the TRM.

SPRS614B (FEBRUARY 2012) has two empty boxes:

Table 8-24 No. 16

Table 8-10 No. 10

Both of which refer to a note: CK/DQS spacing set to ensure proper differential impedance. Again, I have not been able to find this impedance specified anywhere in the document.

It would be good to know what the proper differential impedance is. I have seen the documentation of other similar microprocessors a requirement of 75-95 ohm differential, this leads me to believe that it isn't terribly critical (assuming that the single-ended requirements are met), but I would like some confirmation on this .

A related question, or request for confirmation: The clock termination resistors (Rcp) and address termination resistors (Rtt) must be 60 ohm to comply with 8-24 Nos. 21 and 22, correct? 

  • 0
    TI__Intellectual 1670 points

    In PCB traces, differential signals travel more like two single ended signals.  This is because of two things.  First, the PCB traces are rarely as tightly coupled as they would be if they were twisted pair wiring or other cable assembly, and two, the ground plane interaction with the signals is much stronger than the interaction between signals, so really they're more like two single ended signals with a weak differential coupling.  Google "Lee Ritchey" or any other high speed expert and they'll agree with those statements.

    What this means is that the single ended impedance is much more critical than the differential impedance, which is why we don't give a tolerance for the diff impedance.  The note on PCIe and SATA gives a +/-20% tolerance on those signals for the differential impedance.  This is a decent number to apply to DDR as well if you want a tolerance, but if you meet the single ended impedance and the trace spacing required, the diff. impedance isn't likely to give you any trouble.

    60 ohms is a fine target for the single ended impedance.

    Yes, the values you state for the resistor are "Zo", which is defined in table 8-18 as the board single ended impedance.  This doesn't apply to the DDRx_VTP resistor, which is always 50 ohms.

    I hope that answers your question.  Have a great weekend!

  • 0 in reply to KevenC
    Intellectual 380 points

    Hello Keven,

    I just came across this discussion. I am working with AM3894/DM8168. According to the datasheet, Zo can be 50 to 75 ohms. Does it mean we can choose any value in this range that works best with the PCB stack up ? Does it require any setting in the software ?

    Also, is the impedance setting for CLK+/-, ADDR,CTRL and DQS+/-, DQ, DM signals ? Please clarify.


    Thanks,

    Lakshmi