• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 104 subscribers
  • Views 711 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC Sample and Hold Period

Okayama Gou
Intellectual 930 points
Other Parts Discussed in Thread: TMS320VC5507

Dear,

Could someone give me your advise for following?

  Device: TMS320VC5507ZHH

Following description in spru586b.pdf, TMS320VC5507/5509 DSP ADC Reference Guide, confused me.

In page 8,
 ADC Sample and Hold Period = (1/(ADC Clock)) / (2 x (CONVRATEDIV + 1 + SAMPTIMEDIV))
 [must be greater than or equal to 40us]

In page 13,
 ADC Sample and Hold Period = (ADC Clock Period) x (2 x (CONVRATEDIV + 1 + SAMPTIMEDIV))

Above 2 fomula are inconsistency.
Because (1/(ADC Clock Freq)) = (ADC Clock Period)

<< My Question >>:
  I think "In page 13" is right.
  If so, I think the "In page 8" should be described as following.
  Am I right?

 ADC Sample and Hold Period = (1/(ADC Clock)) x (2 x (CONVRATEDIV + 1 + SAMPTIMEDIV))
 [must be greater than or equal to 40us]

 

Page 8.

Page 13.

 


Thank you and Best regards,
Okayama

 

  • 0
    TI__Mastermind 23785 points

    Yes. Thanks for pointing it out.

    I have filed a report for update.

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 120 points

    Hi,

    I have some confuse about the example in the reference guide. Could you give me some adive?

    TMS320C55x Chip Support Library API Reference Guide SPRU433G

    In page 3-7,

    Example int i=7,j=15,k=1;
    ADC_setFreq(i,j,k);
    /* This example sets the ADC sampling frequency */
    /* to 21.5 KHZ, given a 144 MHZ clockout frequency */

    According to the formula：

    ADC Clock = (CPU Clock) / (CPUCLKDIV + 1)=144M / (7+1)=18M
    ADC Conversion Clock = (ADC Clock) / (2 * (CONVRATEDIV + 1))=18M / ( 2*(15+1) )=9/16 M

    ADC Sample and Hold Period =

    (1 / (ADC Clock))* (2 * (CONVRATEDIV + 1 + SAMPTIMEDIV)) = ( 1/18M )*( 2*( 15+1+1 ) )=17/9 us

    ADC Total Conversion Time =
    (ADC Sample and Hold Period) + (13 * (ADC Conversion Clock Period)) = ( 17/9 ) + ( 13*( 16/9 ) ) = 25 us

    my question:

     1、ADC Sample and Hold Period must be greater than or equal to 40us, but why the example result is 17/9 us？

    2、In the last of the example , the annotation is： /* This example sets the ADC sampling frequency to 21.5 KHZ */   but the result that I  calculate is 40KHZ (1/ADC Sample and Hold Period) . Am i right?

     

    In addition，in the following article:

    Programming the TMS320VC5509 ADC Peripheral

    In page 5,

    In the ADC Keypad Example, when the sysclkdiv value is 2, the ADC Conversion Clock value is 24MHZ, which is greater  than 2MHz not less or equal to 2MHZ, why?

  • 0 in reply to Yangmm
    TI__Genius 12575 points

    Hi,

      While we are look at this, suggestion is to open up a new thread and post your question over there.

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Prodigy 120 points

    Hi,

    Now I post my question over here.

    1.  TMS320C55x Chip Support Library API Reference Guide SPRU433G

    In page 3-7,

    2.  Programming the TMS320VC5509 ADC Peripheral

    In page 5,

    That's  the question  that I referenced in the  above.

    Thanks for giving the answer to me .

  • 0 in reply to Yangmm
    TI__Genius 12575 points

    Hi,

      Yes, Looks like there seems to be an issue in the documenation. Will file a report for correction.

      Suggest you to use the right parameters to acheive the correct ADC sample and hold  period.

    Regards

     Vasanth