The datasheet for the DM8148 says L1P RAM has EDC and L2 RAM has ECC. For my application, I am not using DSP/BIOS and I am turning off all cache (L1D, L1P and L2). However, I cannot find mention of registers for controlling EDC/ECC.
However, I have seen that other devices with EDC/ECC have such registers (see Table 5-11 in sprs438e for TMS320TCI6484, or Table 5-13 in sprs552h for TMS320C6474, or Table 11-5 in sprugw0b for TMS320C66x). In at least some of those devices, the EDC/ECC must be enabled in software if L1P/L2 is used as RAM.
I cannot find anything about this in SPRS647C, SPRUFK5A, SPRUGZ8A.
(1) Is there anything that I need to do to enable EDC/ECC for the C674x's internal RAM?
As far as I can tell from SPRUFE8, an L1P parity error will cause an Instruction Fetch Exception, so the IFX bit will be set in the Internal Exception Report Register (IERR). However, section 6.5.1 lists several other "fetch errors".
(2) Is is possible to differentiate between these different causes?
Thanks
Michael
