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PCIe issue - Cannot write to Integra RAM ( OCMC SRAM ) from separate 6678 DSP connected via the PCIe bus

BradP
Prodigy 120 points

We have an TMS320C6A8168 Integra device connected to a separate TMS3206678 DSP via a PCIe bus. The Integra is setup as a Root Complex and the attached DSP is setup as an End Point. We have been able to write and read to and from the 6678 DSP L3 memory from the Integra. We have been able to write and read from the DSP into 4 general purpose registers in the PCIe register space ( 0x51000070, 0x51000074, 0x51000078, 0x5100007C ) in the Integra. However, when we change the Integra mapping to write to the Integra internal OCMC SRAM from the external DSP, it does not work. We have a PCIe bus analyzer that is showing all the correct PCIe bus traffic. We are suspecting that we do not have something setup correctly in the Integra to allow the L3 bus access from the PCIe module. According to Table 5-1 of the sprs680a.pdf, the PCIe Gen2 as a master is connected directly to the OCMC memory via the L3 bus. Is there anything you can recommend that we may have not setup correctly to make this work.

  • 0
    TI__Mastermind 25055 points

    Hello,

    Here is some feedback from our Design team:

    In this scenario the C6A device is RC and DSP chip is EP.  DSP (EP) is initiating a transfer to RC (C6A).  The C6A is RC and there can be no address translation in RC.

    Please check that the EP uses its outbound address translation to change the address to map to OCMC address before sending on the PCIE link to RC(C6A).   The RC(C6A) will not do any address translation.

    Regards,
    Marc

  • 0 in reply to MarcPyne
    Prodigy 120 points

    I think this does answer our question. I am assumming that we would set up our RC per paragraph 2.6.2.3 of the SPRUGS6A document. This paragraph basicly describes how to use BAR1 to gate the OCMC RAM actual addresses straight into the RC from the EP with no address translation.

    Related questions:

    Is this inbound RC address translation something that should work on the Integra part and, if so, will it be fixed on future releases of the part?

    If we wanted to configure our 6678 DSP to a RC would the inbound translation work for it?

     

  • 0 in reply to BradP
    TI__Mastermind 25055 points

    Hello,

    Here are some answers to your followup questions:

    As of now inbound translation in the C6A device as RC is not supported, and I have not heard of any current plans to add this in the future.

    I'm not familiar with the 6678 DSP, but if the C6A is in EP mode, inbound translation is possible in the C6A.

    Regards,
    Marc

  • 0 in reply to BradP
    TI__Genius 12065 points

    Regarding to the following question:

    "If we wanted to configure our 6678 DSP to a RC would the inbound translation work for it?"

    The inbound translation should be working in both RC and EP modes for C6678 device. We can set 1 to IB_XLT_EN bit in the CMD_STATUS register to enable the inbound translation and setup the other related registers for the correct address translation as mentioned in the user guide.

    If the C6678 is set as RC, only BAR1 could be used for the inbound translation. But it is not limited to the usage as mentioned in the 2.6.2.3 of the SPRUGS6 document. There are some examples about the inbound translation in the section 3.2 of the PCIe use case document (sprabk8) . 

    As Marc mentioned, if the C6678 as RC is working with C6A as EP, then we could setup the outbound translation in C6678 (RC) and inbound translation in C6A (EP) for the memory transactions initiated from RC to EP. And we could setup the inbound translation in C6678 (RC) and outbound translation in C6A (EP) for the memory transactions initiated from EP to RC.

    Sincerely,

    Steven


  • 0 in reply to MarcPyne
    Prodigy 120 points

    We have changed our test setup so that the outbound translation from the 6678 DSP to the Integra maps directly to the 0x40300000 address space on the PCIe bus. We have verified with our PCIe analyzer that the memory writes to address space 0x40300000 are occurring correctly on the PCIe bus at the Integra. We have cleared the IB_XLT_EN  bit in the CMD_STATUS register so that no inbound translation should be happening in the Integra PCIe interface. We are still not getiing any writes into the 0x40300000 space in the Integra. We also tried the inbound setup such that the IB_XLT_EN  bit in the CMD_STATUS register is set and the BAR1 register was set to the 0x40300000 and the IB_BAR set of registers were set to point to BAR1 with all other offsets to zero. This did not work either. We are able to write and read the 0x40300000 space from the ARM side of the L3 bus.

    Has anyone tried this inbound write process with an Integra part an if so could we get sample code for this?

    Are there any other setups we need to perform to allow this inbound PCIe write process to the Integra 0x40300000 address space?

     

  • 0 in reply to BradP
    Prodigy 120 points

    We are still waiting on a response to this issue. As we have now selected the Davinci version ( instead of the Integra ) and reconfirmed our use of the PCIe bus, we really need the inbound PCIe write functionality. We need a way to perform writes from an external device or devices into the internal Davinci memory , either DDR3 or SRAM, over the PCIe bus. Thanks for your help.